Pad arrangement of driver IC chip for LCD and related circuit pattern structure of TAB package

• US 20060097286A1
• Filed: 11/07/2005
• Published: 05/11/2006
• Est. Priority Date: 11/09/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Si-Hoon, Chung, Ye-Chung
• Granted Patent: US 7,459,779 B2
• Time in Patent Office: Days
• US Class Current: 257/203
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]

Abstract

Output pads on an integrated circuit (IC) chip are arranged along a first longer side and are arranged along a second longer side with input pads. The output pads are connected to respective output patterns formed on top and bottom surfaces of a base film. All the output patterns may pass over the first longer side. Alternatively, the output patterns connected to the output pads at the second longer side may pass over a shorter side. These pattern structures establish an effective pad arrangement without increasing the size of a TAB package, yet allowing reduced the chip size.

Claims

1. An LCD driver integrated circuit chip comprising:

a first longer side, a second longer side, a pair of shorter sides, and a plurality of input/output pads arranged thereon,

wherein the plurality of input/output pads include first output pads arranged along the first longer side, and second output pads arranged along the second longer side.

2. The LCD driver integrated circuit chip of claim 1, wherein the first output pads and the second output pads are located at offset longitudinal positions along the respective longer sides.

3. The LCD driver integrated circuit chip of claim 1, wherein the first output pads and the second output pads are located at corresponding longitudinal positions along the respective longer sides.

4. The LCD driver integrated circuit chip of claim 1, wherein the number of the second output pads is smaller than the number of the first output pads.

5. The LCD driver integrated circuit chip of claim 1, wherein the input/output pads further include third output pads arranged along at least one of the pair of shorter sides.

6. The LCD driver integrated circuit chip of claim 1, wherein the input/output pads further include input pads arranged along the second longer side.

7. The LCD driver integrated circuit chip of claim 1, further in combination with a film bearing a circuit pattern electrically connectable to at least one of the output pads and routable over the surface of the LCD driver integrated circuit chip.

8. A package comprising:

an integrated circuit chip including a first longer side, a second longer side opposite the first longer side, a pair of shorter sides, and a plurality of input/output pads arranged thereon, the input/output pads having first output pads arranged along the first longer side and second output pads arranged along the second longer side; and

a base film including a top surface, a bottom surface opposite the top surface, first output patterns formed on one of the top and bottom surfaces, and second output patterns formed on the other of the top and bottom surfaces, the first output patterns being electrically connectable to the first output pads and the second output patterns being electrically connectable to the second output pads, the first and second output patterns being directed to pass over the first longer side.

9. The package of claim 8, wherein the first output patterns are formed on the bottom surface of the base film, and the second output patterns are formed on the top surface of the base film.

10. The package of claim 9, wherein the integrated circuit chip further includes conductive bumps formed on the respective first output pads.

11. The package of claim 10, wherein each of the first output patterns joins a corresponding one of the conductive bumps on the first output pads.

12. The package of claim 9, wherein the integrated circuit chip further includes conductive bumps formed on the respective second output pads.

13. The package of claim 12, wherein each of the second output patterns includes a major part formed on the top surface of the base film, a minor part formed on the bottom surface of the base film, and a connection via formed through the base film to connect the major part and the minor part.

14. The package of claim 13, wherein each of the minor parts of the second output patterns joins a corresponding one of the conductive bumps on the second output pads.

15. The package of claim 8, wherein the first output pads and the second output pads are located at offset longitudinal positions along the respective longer sides.

16. The package of claim 8, wherein the first output pads and the second output pads are located at corresponding longitudinal positions along the respective longer sides.

17. The package of claim 8, wherein the first output patterns and the second output patterns pass in interleaved relation over the first longer side.

18. The package of claim 8, wherein the number of the second output pads is smaller than the number of the first output pads.

19. The package of claim 8, wherein the input/output pads further include third output pads arranged along at least one of the shorter sides.

20. The package of claim 19, wherein the base film further includes third output patterns arranged to electrically connect to the third output pads and to pass over the at least one of the shorter sides.

21. The package of claim 8, wherein the input/output pads further include input pads arranged along the second longer side.

22. The package of claim 21, wherein the base film further includes input patterns arranged to electrically connect to the input pads and to pass over the second longer side.

23. A package comprising:

an integrated circuit chip including a first longer side, a second longer side, a pair of shorter sides, and a plurality of input/output pads arranged thereon, the input/output pads having first output pads arranged along the first longer side, and second output pads arranged along the second longer side; and

a base film including a top surface, a bottom surface opposing to the top surface, first output patterns formed on the bottom surface, and second output patterns formed on the bottom surface, the first output patterns being electrically connectable to the first output pads and directed to pass over the first longer side, the second output patterns being electrically connectable to the second output pads and directed to pass over at least one of the shorter sides.

24. The package of claim 23, wherein the integrated circuit chip further includes conductive bumps formed on the respective first and second output pads.

25. The package of claim 24, wherein the first and second output patterns are joined to the conductive bumps on the respective output pads.

26. The package of claim 23, wherein the number of the second output pads is smaller than the number of the first output pads.

27. The package of claim 23, wherein the plurality of input/output pads further include input pads arranged along the second longer side.

28. The package of claim 27, wherein the base film further includes input patterns arranged to electrically connect to the input pads and to pass over the second longer side.

29. The package of claim 23, wherein a pitch of the second output patterns is smaller than a pitch of the second output pads.