Semiconductor memory devices including a vertical channel transistor and methods of manufacturing the same

• US 20060097304A1
• Filed: 06/13/2005
• Published: 05/11/2006
• Est. Priority Date: 11/08/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Dong-gun, Lee, Choong-ho, Lee, Chul, Yoon, Jae-man, Yi, Moon-suk
• Granted Patent: US 7,531,412 B2
• Time in Patent Office: Days
• US Class Current: 257/307
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

Claims

1. A semiconductor memory device comprising:

a semiconductor substrate;

a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate;

respective surrounding gate electrodes surrounding ones of the pillars;

a first source/drain region in the semiconductor substrate between adjacent ones of the pillars;

a second source/drain region in an upper portion of at least one of the adjacent pillars;

a buried bit line in the first source/drain region and electrically coupled to the first source/drain region; and

a storage node electrode on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

2. The semiconductor memory device of claim 1, further comprising a word line contacting with ones of the surrounding gate electrodes and extending in a cross-wise pattern relative to the bit line.

3. The semiconductor memory device of claim 2, further comprising respective conductive spacers between the word line and the ones of the surrounding gate electrodes contacting the word line.

4. The semiconductor memory device of claim 3, wherein the conductive spacers are on an upper outside surface of the surrounding gate electrodes.

5. The semiconductor memory device of claim 3, wherein a conductive film for the conductive spacers and the word line comprises a transition metal film of tungsten (W), cobalt (Co), nickel (Ni), and/or titanium (Ti);

a transition metal silicide film of tungsten silicide (WSi_x), cobalt silicide (CoSi_x), nickel silicide (NiSi_x), and/or titanium silicide (TiSi_x); and

/or a tungsten nitride film (WN)/tungsten film (W).

6. The semiconductor memory device of claim 1, wherein the first and second source/drain regions are electrically insulated from the surrounding gate electrodes.

7. The semiconductor memory device of claim 1, wherein a dielectric material is located between adjacent ones of the pillars to electrically insulate the adjacent ones of the pillars.

8. The semiconductor memory device of claim 1, wherein the bit line is a transition metal silicide film.

9. The semiconductor memory device of claim wherein:

the plurality of pillars are formed in a matrix and are separated from each other by a predetermined distance;

the first source/drain region is a drain region of a vertical channel transistor; and

the second source/drain region is a source region of the vertical channel transistor.

10. A semiconductor memory device comprising:

a semiconductor substrate including a plurality of pillars separated from each other by a predetermined distance;

a device isolation film between the pillars;

respective surrounding gate electrodes electrically insulated from the pillars and surrounding an upper outside of each pillar;

first source/drain regions formed in an upper portion of respective ones of the pillar;

a second source/drain region formed in the semiconductor substrate between adjacent ones of the pillars;

a buried bit line, interposed between the second source/drain region and the device isolation film, electrically contacting the second source/drain region;

a word line formed in a cross-wise pattern with the bit line and electrically connected to ones of the surrounding gate electrodes;

contact pads, formed on respective ones of the first source/drain regions and contacting the respective ones of the first source/drain regions; and

storage node electrodes formed on the contact pads.

11. The semiconductor memory device of claim 10, further comprising conductive spacers between an upper outside of the surrounding gate electrodes and the word line.

12. The semiconductor memory device of claim 11, wherein a conductive film for the conductive spacers and the word line is a transition metal film formed of tungsten (W), cobalt (Co), nickel (Ni), and/or titanium (Ti);

a transition metal silicide film formed of tungsten silicide (WSi_x), cobalt silicide (CoSi_x), nickel silicide (NiSi_x), and/or titanium silicide (TiSi_x); and

/or a tungsten nitride film (WN)/tungsten film (W).

13. The semiconductor memory device of claim 10, wherein the bit line surrounds a lower outside of respective ones of the pillars.

14. The semiconductor memory device of claim 10, wherein the bit line is a transition metal silicide film.

15. A method of manufacturing a semiconductor memory device, the method comprising:

forming a plurality of semiconductor material pillars in a spaced relationship on a semiconductor substrate;

forming respective surrounding gate electrodes on ones of the pillars;

forming a first source/drain region in the semiconductor substrate between adjacent ones of the pillars;

forming a bit line in the first source/drain region and electrically coupled to the first source/drain region; and

forming a second source/drain region in an upper portion of at least one of the adjacent ones of the pillars.

16. The method of claim 15 wherein forming a plurality of semiconductor material pillars includes:

forming a pad oxide film and a hard mask pattern on the semiconductor substrate;

forming a plurality of pillars to a smaller width than the width of the hard mask pattern by etching the pad oxide film and the semiconductor substrate conformally to the hard mask pattern; and

isolating the pillars by etching the semiconductor substrate between the pillars to a predetermined depth; and

wherein forming a bit line includes forming the bit line to surround outer surfaces of ones of the pillars; and

wherein the method further comprises;

forming a word line in a cross-wise pattern with the bit line so that the word line is electrically connected to ones of the surrounding gate electrodes;

removing the hard mask pattern; and

wherein forming a second source/drain region comprises forming the second source/drain region after removing the hard mask pattern to expose the upper portion.

17. The method of claim 16, wherein forming a plurality of pillars includes:

etching the pad oxide film and the semiconductor substrate to a predetermined depth using the hard mask pattern; and

etching sidewalls of the semiconductor substrate to a predetermined width.

18. The method of claim 17, wherein isolating the pillars by etching the semiconductor substrate to a predetermined depth includes anisotropically etching the semiconductor substrate to a depth of about 800 Å

to about 1,500 Å

.

19. The method of claim 17, wherein etching sidewalls of the semiconductor substrate includes anisotropically etching the sidewalls to a width of about 200 Å

to about 300 Å

using the hard mask pattern as an etching mask.

20. The method of claim 19, wherein the sidewalls of the semiconductor substrate are anisotropically etched by plasma wet etching and/or chemical dry etching.

21. The method of claim 16, wherein forming the surrounding gate electrodes includes:

forming a gate oxide film on the pillars and surfaces of the semiconductor substrate between the pillars;

depositing a conductive film on the gate oxide film; and

etching back the conductive film so that the conductive film remains on sidewalls of the pillars.

22. The method of claim 16, wherein forming the first source/drain region includes implanting an ionic impurity in an exposed portion of the semiconductor substrate between the pillars by the hard mask pattern and the surrounding gate electrodes.

23. The method of claim 16, wherein forming the bit line in the first source/drain region includes:

forming a groove in the first source/drain region to a shallower depth than the drain region;

forming a dielectric film at sidewalls of the groove;

selectively forming a conductive line in the groove; and

etching a predetermined portion of the conductive line to form the bit line.

24. The method of claim 23, wherein forming the groove includes:

coating a dielectric film on a surface of the semiconductor substrate;

etching back the dielectric film so that the dielectric film surrounds an outer surface of the surrounding gate electrodes and a predetermined portion of the first source/drain region is exposed; and

etching the exposed portion of the first source/drain region to a predetermined depth using the etched-back dielectric film as an etching mask.

25. The method of claim 23, wherein forming the conductive line includes:

depositing a transition metal film on a surface of the semiconductor substrate including the groove;

selectively forming a transition metal silicide film by heating so that the transition metal film reacts with underlying semiconductor substrate material; and

removing an unreacted portion of the transition metal film.

26. The method of claim 23, wherein etching a predetermined portion of the conductive line to form the bit line includes:

depositing a dielectric film on the semiconductor substrate where the conductive line is formed;

forming a dielectric spacer by etching back the dielectric film; and

etching the conductive line using the dielectric spacer as an etching mask, and

wherein the dielectric film is formed to a thickness selected to provide a filled space between adjacent ones of the pillars and/or a space between the pillars as viewed in the x-axis direction.

27. The method of claim 16, wherein isolating the pillars includes etching the semiconductor substrate between the pillars to a depth of about 1,000 Å

to about 1,000 Å

using the bit line as an etching mask.

28. The method of claim 16, further comprising, after isolating the pillars and before forming the word line, forming respective conductive spacers on an upper outside of ones of the surrounding gate electrodes to provide conductivity of the ones of the surrounding gate electrodes.

29. The method of claim 28, wherein forming the conductive spacers includes:

forming on the semiconductor substrate a dielectric film to a substantially same height as the hard mask pattern;

removing the dielectric film to a predetermined depth so that sidewalls of the hard mask pattern and upper outsides of the surrounding gate electrodes are exposed;

depositing a conductive film on the semiconductor substrate including the dielectric film removed to a predetermined depth; and

etching back the conductive film to form the conductive spacers on the exposed sidewalls of the hard mask pattern and the exposed upper outsides of the surrounding gate electrodes.

30. The method of claim 29, wherein removing the dielectric film includes removing the dielectric film by a wet etch-back process.

31. The method of claim 29, wherein the conductive film for the conductive spacers comprises a transition metal film formed of tungsten (W), cobalt (Co), nickel (Ni), and/or titanium (Ti);

a transition metal silicide film formed of tungsten silicide (WSi_x), cobalt silicide (CoSi_x), nickel silicide (NiSi_x), and/or titanium silicide (TiSi_x); and

/or a tungsten nitride film (WN)/tungsten film (W).

32. The method of claim 29, wherein the conductive spacers are formed to a lower height than the hard mask pattern.

33. The method of claim 16, wherein forming the word line includes:

forming, on the semiconductor substrate including the conductive spacer, a first dielectric film to a substantially same height as the hard mask pattern;

forming a second dielectric film on the first dielectric film;

forming a photoresist pattern on the second dielectric film in a cross-wise pattern with the bit line so that the hard mask pattern is exposed;

etching the first and second dielectric films to a predetermined depth using the photoresist pattern as an etching mask;

removing the photoresist pattern;

depositing a conductive film on the semiconductor substrate including the etched first and second dielectric films with the photoresist pattern removed; and

etching back the conductive film to a lower height than the hard mask pattern to form the word line.

34. The method of claim 33, wherein the first and second dielectric films are formed of a material having etching selectivity with respect to the hard mask pattern.

35. The method of claim 33, wherein etching the first and second dielectric films includes etching the first and second dielectric films to a depth that exposes a portion of the conductive spacers.

36. The method of claim 33, wherein the conductive film for the word line comprises a transition metal film formed of tungsten (W), cobalt (Co), nickel (Ni), ande/or titanium (Ti);

a transition metal silicide film formed of tungsten silicide (WSi_x), cobalt silicide (CoSi_x), nickel silicide (NiSi_x), and/or titanium silicide (TiSi_x); and

/or a tungsten nitride film (WN)/tungsten film (W).

37. The method of claim 33, wherein etching back the conductive film to form the word line includes:

initially etching back the conductive film so that the hard mask pattern is exposed; and

further etching back the conductive film to a lower height than the hard mask pattern.

38. The method of claim 16, wherein forming the second source/drain region includes implanting ionic impurities in the pillars on which the hard mask pattern is removed.

39. The method of claim 16, further comprising, after forming the second source/drain region:

forming a contact pad on the second source/drain region and electrically connected thereto; and

forming a storage node electrode on the contact pad and electrically connected thereto; and

wherein the contact pad is electrically insulated from the conductive spacers and the gate electrodes.

40. A method of manufacturing a semiconductor memory device, the method comprising:

forming on a semiconductor substrate a hard mask pattern defining a pad oxide film and an active region;

forming a plurality of pillars by etching the pad oxide film to a predetermined depth and the semiconductor substrate to a predetermined width using the hard mask pattern as an etching mask;

forming a surrounding gate electrode on an outer surface of ones of the pillars;

forming a drain region in the semiconductor substrate between the ones of the pillars;

selectively forming a conductive line in the drain region;

forming a dielectric spacer surrounding the hard mask pattern;

forming a bit line by etching the conductive line using the dielectric spacer as an etching mask;

isolating the ones of the pillars by etching the semiconductor substrate using the bit line as an etching mask;

forming a conductive spacer on an upper outside of the surrounding gate electrode;

forming a word line contacting the conductive spacer in a cross-wise pattern with the bit line;

removing the hard mask pattern;

forming a source region in the pillars where the hard mask pattern is removed;

forming a contact pad on the source region so that the contact pad contacts the source region and is electrically insulated from the conductive spacer and the gate electrode; and

forming a storage node electrode on the contact pad.

41. The method of claim 40, wherein forming the source region comprises:

depositing a dielectric film on the semiconductor substrate in a region where the hard mask pattern is removed;

forming a dielectric spacer at sidewalls of the conductive spacer by anisotropically etching the dielectric film to expose the pad oxide film;

etching the pad oxide film using the dielectric spacer as an etching mask; and

implanting an impurity in exposed portions of the ones of the pillars.