Gate dielectric antifuse circuits and methods for operating same

• US 20060097345A1
• Filed: 12/02/2005
• Published: 05/11/2006
• Est. Priority Date: 08/31/2000
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Kenneth W.
• Application Number:
  US11/292,653
• Publication Number:
  US 20060097345A1
• Time in Patent Office: Days
• US Class Current: 257/530
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A number of antifuse support circuits and methods for operating them are disclosed according to embodiments of the present invention. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode. An antifuse having a first terminal coupled to the common bus line is selected to be programmed by a control transistor in a program driver circuit coupled to a second terminal of the antifuse. The program driver circuit has a high-voltage transistor with a diode coupled to its gate to bear a portion of the elevated voltage after the antifuse has been programmed. The program driver circuit also has an impedance transistor between the high-voltage transistor and the control transistor to reduce leakage current and the possibility of a snap-back condition in the control transistor. A read circuit includes a transistor coupled between a read voltage source and the second terminal to read the antifuse in an active mode. The common bus line may be coupled to a reference voltage through a common bus line driver circuit in the active mode to pass current to or from the read circuit. The common bus line driver circuit has a control transistor and a high-voltage transistor with a diode coupled to its gate to bear the elevated voltage on the common bus line during the programming mode. The read circuit may have a latch circuit to latch a state of the antifuse in a sleep mode. A floating well driver logic circuit raises the voltage potential of wells and gate terminals of p-channel transistors in the read circuit during the programming mode to reduce current flow from the common bus line.

Claims

1. A transistor comprising:

a p-type halo in a source side of a p-type substrate;

an n-type lightly doped drain in the halo;

an n+-type source diffusion region in the lightly doped drain; and

an n+-type drain diffusion region in a drain side of the substrate.

2. The transistor of claim 1, further including:

a drain terminal connected to the drain diffusion region;

a source terminal connected to the source diffusion region;

a layer of gate dielectric over the substrate between the drain diffusion region and the source diffusion region;

a polysilicon gate over the layer of gate dielectric;

an electrode over the polysilicon gate;

a spacer on sides of the gate dielectric, the polysilicon gate, and the electrode; and

a gate terminal connected to the electrode.

3. A method of forming a transistor comprising:

forming a p-type halo in a source side of a p-type substrate;

forming an n-type lightly doped drain in the halo;

forming an n+-type source diffusion region in the lightly doped drain; and

forming an n+-type drain diffusion region in a drain side of the substrate.

4. The method of claim 3, further including:

connecting a drain terminal to the drain diffusion region;

connecting a source terminal to the source diffusion region;

forming a layer of gate dielectric over the substrate between the drain diffusion region and the source diffusion region;

forming a polysilicon gate over the layer of gate dielectric;

forming an electrode over the polysilicon gate;

forming a spacer on sides of the gate dielectric, the polysilicon gate, and the electrode; and

connecting a gate terminal to the electrode.

5. A transistor comprising:

an n-type well in a drain side of a p-type substrate;

an n+-type drain diffusion region in the well;

a p-type halo in a source side of the substrate;

an n-type lightly doped drain in the halo; and

an n+-type source diffusion region in the lightly doped drain.

6. The transistor of claim 5, further including:

a drain terminal connected to the drain diffusion region;

a source terminal connected to the source diffusion region;

a layer of gate dielectric over the substrate between the drain diffusion region and the source diffusion region;

a polysilicon gate over the layer of gate dielectric;

an electrode over the polysilicon gate;

a spacer on sides of the gate dielectric, the polysilicon gate, and the electrode; and

a gate terminal connected to the electrode.

7. A method of forming a transistor comprising:

forming an n-type well in a drain side of a p-type substrate;

forming an n+-type drain diffusion region in the well;

forming a p-type halo in a source side of the substrate;

forming an n-type lightly doped drain in the halo; and

forming an n+-type source diffusion region in the lightly doped drain.

8. The method of claim 7, further including:

connecting a drain terminal to the drain diffusion region;

connecting a source terminal to the source diffusion region;

forming a layer of gate dielectric over the substrate between the drain diffusion region and the source diffusion region;

forming a polysilicon gate over the layer of gate dielectric;

forming an electrode over the polysilicon gate;

forming a spacer on sides of the gate dielectric, the polysilicon gate, and the electrode; and

connecting a gate terminal to the electrode.

9. An integrated circuit comprising:

an external pin;

a common bus line coupled to the external pin;

an antifuse bank coupled to the common bus line, the antifuse bank including a plurality of antifuses; and

a common bus line driver circuit including;

a high-voltage transistor having a first terminal coupled to the common bus line, a control terminal, and a second terminal;

a diode coupled between the control terminal and a reference voltage; and

a control transistor coupled between the second terminal and a voltage reference.

10. The integrated circuit of claim 9, wherein:

the high-voltage transistor includes an n-well drain transistor having a drain terminal coupled to the common bus line, a control terminal coupled to the diode, and a source terminal coupled to the control transistor;

the diode includes;

a first diode including an anode coupled to a voltage supply and a cathode coupled to the control terminal of the n-well drain transistor; and

a second diode including a cathode coupled to the control terminal of the n-well drain transistor and an anode coupled to a voltage reference to withstand a high voltage on the control terminal of the n-well drain transistor;

the control transistor is coupled between the second terminal and a reference voltage and further includes a control circuit to switch on the control transistor to couple the common bus line to the ground voltage reference and to switch off the control transistor to permit an elevated voltage on the common bus line.

11. A method of operating an integrated circuit comprising:

coupling an elevated voltage through an external pin to a common bus line in the integrated circuit to program an antifuse coupled to the common bus line;

switching off a control transistor in a common bus line driver circuit coupled between the common bus line and a voltage reference to substantially prevent current flow from the common bus line;

bearing a portion of the elevated voltage across a high-voltage transistor having a first terminal coupled to the common bus line, a control terminal, and a second terminal coupled to the control transistor;

bearing a portion of the elevated voltage between a diode and the control terminal of the high-voltage transistor; and

switching on the control transistor to couple the common bus line to the voltage reference to read the antifuse.

12. The method of claim 11, wherein:

switching off a control transistor includes switching off a control transistor with a control circuit in a common bus line driver circuit coupled between the common bus line and a voltage reference to substantially prevent current flow from the common bus line;

bearing a portion of the elevated voltage across a high-voltage transistor includes bearing a portion of the elevated voltage across an n-well drain transistor having a drain terminal coupled to the common bus line, a control terminal coupled to a diode, and a source terminal coupled to the control transistor;

bearing a portion of the elevated voltage between a diode and the control terminal includes bearing a portion of the elevated voltage between the control terminal of the n-well drain transistor, a first diode including an anode coupled to a voltage supply and a cathode coupled to the control terminal of the n-well drain transistor, and a second diode including a cathode coupled to the control terminal of the n-well drain transistor and an anode coupled to a reference voltage; and

switching on the control transistor includes switching on the control transistor with the control circuit to couple the common bus line to the voltage reference to read the antifuse.

13. A circuit comprising:

a high-voltage transistor including;

a well of a first conductivity type in a substrate of a second conductivity type;

a drain diffusion region of the first conductivity type in the well, the drain diffusion region being coupled to an elevated voltage source;

a source diffusion region of the first conductivity type in the substrate;

a layer of gate dielectric over the substrate; and

a gate electrode over the gate dielectric;

a diode coupled between the gate electrode and a reference voltage to hold a voltage on the gate electrode caused by a charge transfer across the gate dielectric due to the elevated voltage source;

a support circuit coupled to the source diffusion region.

14. The circuit of claim 13, wherein:

the substrate includes a p-type substrate;

the well includes an n-type well in the p-type substrate;

the drain diffusion region includes an n+-type drain diffusion region in the n-type well;

the source diffusion region includes an n+-type source diffusion region in the p-type substrate;

the gate dielectric includes a layer of oxide;

the gate electrode includes a gate electrode over the layer of oxide;

the diode includes;

a first diode including an anode coupled to a voltage supply and a cathode coupled to the gate electrode of the high-voltage transistor to switch on the high-voltage transistor; and

a second diode including a cathode coupled to the gate electrode of the high-voltage transistor and an anode coupled to a reference voltage to withstand a high voltage on the gate electrode; and

the support circuit includes a control transistor is coupled between the source diffusion region and a ground voltage reference and further includes a control circuit to switch on the control transistor to couple the elevated voltage source to the ground voltage reference and to switch off the control transistor to permit the circuit to bear the elevated voltage.

15. A method comprising:

coupling an elevated voltage to a drain of a high-voltage transistor;

allowing charge to transfer from the drain across a layer of gate dielectric to a gate electrode of the high-voltage transistor; and

allowing the charge to accumulate in the gate electrode to raise a voltage of the gate electrode to a balanced voltage to reduce further charge transfer across the layer of gate dielectric.

16. The method of claim 15, wherein:

coupling an elevated voltage to a drain includes coupling an elevated voltage to an n+-type drain diffusion region in an n-type well in a p-type substrate of a high-voltage transistor;

allowing charge to transfer from the drain includes allowing charge to transfer from the n+-type drain diffusion region across a layer of gate oxide to a gate electrode of the high-voltage transistor; and

allowing the charge to accumulate includes holding the charge in the gate electrode with a first diode including an anode coupled to a voltage supply and a cathode coupled to the gate electrode and a second diode including an cathode coupled to the gate electrode and an anode coupled to a reference voltage to raise a voltage of the gate electrode to a balanced voltage to reduce further charge transfer across the layer of oxide.

17. An antifuse circuit comprising:

an antifuse having a first terminal coupled to a programming voltage supply and a second terminal;

a high-voltage transistor including;

a well of a first conductivity type in a substrate of a second conductivity type;

a drain diffusion region of the first conductivity type in the well, the drain diffusion region being coupled to the second terminal of the antifuse;

a source diffusion region of the first conductivity type in the substrate;

a layer of gate dielectric over the substrate; and

a gate electrode over the gate dielectric;

a diode coupled between the gate electrode and a first reference voltage to hold a voltage on the gate electrode caused by a charge transfer across the gate dielectric due to the programming voltage;

an impedance transistor having a first terminal coupled to the source diffusion region of the antifuse and a second terminal; and

a control transistor having a first terminal coupled to the second terminal of the impedance transistor, a second terminal coupled to a second reference voltage, and a control terminal coupled to a control circuit to switch the control transistor on to couple the second terminal of the anti fuse to the second reference voltage to program the antifuse, and to switch the control transistor off when the antifuse is not being programmed.

18. The antifuse circuit of claim 17, wherein:

the substrate includes a p-type substrate;

the well includes an n-type well in the p-type substrate;

the drain diffusion region includes an n+-type drain diffusion region in the n-type well;

the source diffusion region includes an n+-type source diffusion region in the p-type substrate;

the gate dielectric includes a layer of oxide;

the gate electrode includes a gate electrode over the layer of oxide;

the diode includes;

a first diode including an anode coupled to a voltage supply and a cathode coupled to the gate electrode of the high-voltage transistor to switch on the high-voltage transistor; and

a second diode including a cathode coupled to the gate electrode of the high-voltage transistor and an anode coupled to a reference voltage to withstand a high voltage on the gate electrode;

the control transistor includes an n-channel transistor; and

the impedance transistor includes an n-channel transistor including a gate terminal coupled to the voltage supply.

19. A method of operating an antifuse circuit comprising:

coupling an elevated voltage to a first terminal of an antifuse from a common bus line;

coupling a second terminal of the antifuse to a reference voltage through a control transistor to program the antifuse with current from the common bus line;

switching off the control transistor to uncouple the second terminal of the antifuse from the reference voltage after the antifuse is programmed; and

reducing a voltage on a terminal of the control transistor with an impedance transistor coupled between the second terminal of the antifuse and the terminal of the control transistor to reduce a probability of snap-back in the control transistor.

20. The method of claim 19, wherein:

coupling an elevated voltage includes coupling an elevated voltage from an external pin to a first terminal of an antifuse through a common bus line;

coupling a second terminal of the antifuse includes coupling a second terminal of the antifuse to a ground reference voltage through an n-channel control transistor to program the antifuse with current from the common bus line;

switching off the control transistor includes switching off the n-channel control transistor with a control circuit to uncouple the second terminal of the antifuse from the ground reference voltage after the antifuse is programmed; and

reducing a voltage includes reducing a voltage on a drain terminal of the n-channel control transistor with an n-channel impedance transistor that is switched on and coupled between the second terminal of the antifuse and the drain terminal of the control transistor to reduce a probability of snap-back in the control transistor.

21. A method of operating an antifuse circuit including:

coupling an elevated voltage to a first terminal of an unprogrammed antifuse from a common bus line;

separating a second terminal of the antifuse from a reference voltage with a control transistor that is switched off; and

reducing a voltage on a terminal of the control transistor with an impedance transistor coupled between the second terminal of the antifuse and the terminal of the control transistor to reduce leakage current in the control transistor.

22. The method of claim 21, wherein:

coupling an elevated voltage includes coupling an elevated voltage from an external pin to a first terminal of an antifuse through a common bus line;

separating a second terminal of the antifuse includes separating a second terminal of the antifuse from a ground reference voltage with an n-channel control transistor that is switched off; and

reducing a voltage includes reducing a voltage on a drain terminal of the n-channel control transistor with an n-channel impedance transistor that is switched on and coupled between the second terminal of the antifuse and the drain terminal of the control transistor to reduce leakage current in the control transistor.

23. An antifuse circuit comprising:

an antifuse having a first terminal coupled to an elevated voltage in a programming mode and a reference voltage in an active mode;

a read circuit including a p-channel transistor coupled between a read voltage source and a second terminal of the antifuse to couple the read voltage source to the antifuse to read the antifuse in the active mode; and

a floating well driver logic circuit coupled to a gate terminal and a well of the p-channel transistor to raise a voltage of the gate terminal and the well in the programming mode to substantially prevent current in the p-channel transistor.

24. The antifuse circuit of claim 23, wherein:

the antifuse includes an antifuse having a first terminal coupled to a common bus line, the common bus line being coupled to the elevated voltage in the programming mode and to a ground reference voltage in the active mode;

the read circuit further includes a plurality of p-channel transistors, one of the p-channel transistors being coupled between the second terminal of the antifuse and the floating well driver logic circuit to couple a rising voltage on the second terminal of the antifuse to the floating well driver logic circuit; and

the floating well driver logic circuit further includes a voltage source coupled to a gate terminal and a well of selected ones of the p-channel transistors in the read circuit to raise a voltage of the gate terminals and the wells in the programming mode to substantially prevent current in the selected p-channel transistors.

25. A method of operating an antifuse circuit, comprising:

coupling an elevated voltage to a first terminal of an antifuse in a programming mode and coupling a reference voltage to the first terminal in an active mode;

reading the antifuse in the active mode with a p-channel transistor coupled between a read voltage source and a second terminal of the antifuse; and

raising a voltage of a gate terminal and a well of the p-channel transistor in the programming mode to substantially prevent current in the p-channel transistor.

26. The method of claim 25, wherein:

coupling a reference voltage includes coupling a ground reference voltage to the first terminal in the active mode;

reading the antifuse further includes;

coupling the read voltage source to the second terminal of the antifuse; and

detecting a voltage on the second terminal of the antifuse with an inverter in a read circuit; and

raising a voltage includes;

coupling a rising voltage on the second terminal of the antifuse to a gate terminal and a well of each of a plurality of p-channel transistors in the read circuit.

27. An integrated memory device comprising:

an array of memory cells;

an address decoder;

a plurality of input/output paths;

an input/output control circuit; and

an antifuse circuit including;

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse in a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed in the programming mode;

a common bus line driver circuit to couple the common bus line to a reference voltage during an active mode;

a read circuit coupled to the second terminal of the antifuse to read the antifuse during the active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

a floating well driver logic circuit coupled to the read circuit and the latch circuit to switch off transistors in the read circuit and the latch circuit during the programming mode.

28. An integrated circuit comprising:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse in a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed in the programming mode;

a common bus line driver circuit to couple the common bus line to a reference voltage during an active mode;

means for reading the antifuse during the active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

means for switching off transistors in the latch circuit and in the means for reading the antifuse during the programming mode.