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Method for forming a dual layer, low resistance metallization during the formation of a semiconductor device

  • US 20060097397A1
  • Filed: 11/10/2004
  • Published: 05/11/2006
  • Est. Priority Date: 11/10/2004
  • Status: Abandoned Application
First Claim
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1. A method used during the formation of a semiconductor device, comprising:

  • providing a dielectric layer comprising at least one trench therein;

    forming a first liner to line the trench;

    forming a refractory metal blanket layer on the first liner;

    performing an etch back of the refractory metal blanket layer such that the etched refractory metal layer fills between 5% and 50% of the volume of the trench;

    forming a second liner which contacts the etched refractory metal layer;

    forming a copper metal blanket layer on the second liner; and

    polishing the copper metal blanket layer to result in a polished copper layer which fills the trench and is planarized with an upper surface of the dielectric layer.

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