Method for forming a dual layer, low resistance metallization during the formation of a semiconductor device

• US 20060097397A1
• Filed: 11/10/2004
• Published: 05/11/2006
• Est. Priority Date: 11/10/2004
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Russell, Stephen W.
• Application Number:
  US10/985,635
• Publication Number:
  US 20060097397A1
• Time in Patent Office: Days
• US Class Current: 257/762
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

A method for providing a highly reliable, low resistance interconnect comprises forming a trench in a dielectric layer, forming a first liner in the trench then forming a resilient layer such as a tungsten layer within the trench. The resilient layer is etched back to remove the layer from a horizontal portion of the dielectric outside the trench and to recess the layer within the trench. Next, a second liner and a copper layer are formed in the trench over the resilient layer. The copper layer and exposed portions of the two liners are polished or etched back to result in the interconnect. Variations to this embodiment are also described.

Claims

1. A method used during the formation of a semiconductor device, comprising:

providing a dielectric layer comprising at least one trench therein;

forming a first liner to line the trench;

forming a refractory metal blanket layer on the first liner;

performing an etch back of the refractory metal blanket layer such that the etched refractory metal layer fills between 5% and 50% of the volume of the trench;

forming a second liner which contacts the etched refractory metal layer;

forming a copper metal blanket layer on the second liner; and

polishing the copper metal blanket layer to result in a polished copper layer which fills the trench and is planarized with an upper surface of the dielectric layer.

2. The method of claim 1 wherein the polishing of the copper metal blanket layer is a chemical mechanical polish.

3. The method of claim 1 wherein the etch back of the refractory metal comprises exposing the refractory metal to an etchant comprising a halide.

4. The method of claim 3 wherein the halide-comprising etchant comprise a material selected from the group consisting of sulfur hexafluoride, boron trichloride, and chlorine.

5. The method of claim 1 further comprising polishing the first liner during the polishing of the copper metal blanket layer to result in a first liner which is planarized with the upper surface of the dielectric layer.

6. The method of claim 1 further comprising forming the second liner to contact the first liner.

7. The method of claim 1 further comprising:

forming a conductive region;

providing the dielectric layer over the conductive region;

etching the dielectric layer to expose the conductive region; and

forming the first liner to contact the conductive region,

wherein the refractory metal layer is electrically coupled with the conductive region through the first liner, and the copper layer is electrically coupled to the conductive region through the second liner, the refractory metal layer, and the first liner.

8. A method used to form a conductive interconnect during the formation of a semiconductor device, comprising:

forming a silicon dioxide layer comprising a major surface and an elongated trench;

forming a first conformal liner on the major surface and within the trench;

forming a refractory metal layer within the trench, over the major surface of the silicon dioxide layer, and on the first conformal liner;

performing an etch back on the refractory metal layer to recess the refractory metal layer within the trench and removing the refractory metal layer from over the major surface of the silicon dioxide layer;

subsequent to performing the etch back of the refractory metal layer, forming a second conformal liner on the refractory metal layer;

forming a conformal copper layer on the second conformal liner and within the trench; and

removing the copper layer from over the major surface of the silicon dioxide layer and leaving the copper layer within the trench to form an upper surface of the copper layer which is generally continuous with the major surface of the silicon dioxide layer.

9. The method of claim 8 wherein the etch back of the refractory metal layer leaves sufficient refractory metal to fill the trench to between 5% and 50% of the volume of the trench.

10. The method of claim 8 wherein the removal of the copper layer from over the major surface of the silicon dioxide layer is performed using chemical mechanical planarization.

11. The method of claim 8 wherein the etch back of the refractory metal layer is performed using titanium tetrachloride.

12. The method of claim 8 further comprising forming the first conformal liner from a material selected from the group consisting of titanium, titanium nitride, and tungsten nitride.

13. The method of claim 12 further comprising forming the second conformal liner from at least one material selected from the group consisting of tantalum, tantalum nitride, tantalum silicon nitride, tantalum carbon nitride, tantalum carbide, titanium, titanium nitride, tungsten, tungsten nitride, tungsten carbide, tungsten carbon nitride, and tungsten silicon nitride.

14. The method of claim 9 further comprising removing the first and second conformal liners from over the major surface of the silicon dioxide during the removal of the copper layer from over the major surface.

15. The method of claim 8 further comprising:

forming a conductive layer;

forming the silicon dioxide layer over the conductive layer;

etching the silicon dioxide layer to expose the conductive layer; and

forming the first conformal liner to contact the conductive layer,

wherein the refractory metal layer is electrically coupled with the conductive layer through the first liner, and the copper layer is electrically coupled to the conductive layer through the second liner, the refractory metal layer, and the first liner.

16. A semiconductor device comprising:

a dielectric layer having a major surface and a trench therein;

a refractory metal layer within the trench which fills between 5% and 50% of the volume of the trench; and

a copper layer within the trench over the refractory metal layer, the copper layer comprising an upper surface which is generally continuous with the major surface of the dielectric layer.

17. The semiconductor device of claim 16 further comprising:

a first liner lining the trench under the refractory metal layer; and

a second liner interposed between the copper layer and the refractory metal layer.

18. A semiconductor interconnect comprising, in a vertical cross-section:

a first liner material defining a first elongated interconnect receptacle;

a refractory metal filling a portion of the first elongated interconnect receptacle defined by the first liner;

a second liner material covering the refractory metal and contacting the first liner, wherein the second liner material forms a second elongated interconnect receptacle; and

copper filling the second elongated interconnect receptacle, wherein a cross sectional area of the refractory metal filling the first elongated interconnect receptacle is equal to or less than a cross sectional area of the copper filling the second elongated interconnect receptacle.

19. The semiconductor interconnect of claim 18 further comprising:

the first liner material defining a first contact receptacle; and

the refractory metal filling the contact receptacle defined by the first liner, wherein a cross sectional area of the refractory metal within and directly over the contact receptacle defined by the first liner is greater than a cross sectional area of the copper directly over the contact receptacle.