Method and apparatus for controlling a circuit with a high voltage sense device

• US 20060097770A1
• Filed: 12/23/2005
• Published: 05/11/2006
• Est. Priority Date: 07/08/2004
• Status: Active Grant

• Current Assignee: Donald R. Disney
• Original Assignee: Donald R. Disney
• Inventors: Disney, Donald R.
• Granted Patent: US 7,205,824 B2
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches

Abstract

A control circuit with a high voltage sense device. In one embodiment, an apparatus includes a first transistor disposed in a substrate having a first, a second and a third terminal. The first terminal of the first transistor is to be coupled to an external voltage and the second and third terminals of the first transistor are to be coupled to a ground reference voltage. The apparatus also includes a second transistor disposed in the substrate having a first, a second and a tap terminal. The first terminal of the second transistor is coupled to the first terminal of the first transistor, the second terminal of the second transistor is coupled to the second and third terminals of the first transistor and the tap terminal of the second transistor is coupled to provide a tap voltage that is substantially proportional to a voltage between the first and second terminals of the second transistor up to a pinch-off voltage of the second transistor. The tap voltage is substantially constant and less than the voltage between the first and second terminals of second transistor when the voltage between the first and second terminals of second transistor is greater than the pinch-off voltage of the second transistor.

Claims

1. An apparatus, comprising:

a first transistor disposed in a substrate having a first, a second and a third terminal, the first terminal of the first transistor to be coupled to an external voltage and the second and third terminals of the first transistor to be coupled to a ground reference voltage; and

a second transistor disposed in the substrate having a first, a second and a tap terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the second terminal of the second transistor coupled to the second and third terminals of the first transistor and the tap terminal of the second transistor coupled to provide a tap voltage that is substantially proportional to a voltage between the first and second terminals of the second transistor up to a pinch-off voltage of the second transistor, and wherein the tap voltage is substantially constant and less than the voltage between the first and second terminals of second transistor when the voltage between the first and second terminals of second transistor is greater than the pinch-off voltage of the second transistor.

2. The apparatus of claim 1 wherein the first transistor comprises a metal oxide field effect transistor (MOSFET).

3. The apparatus of claim 1 wherein the second transistor comprises a junction field effect transistor (JFET).

4. The apparatus of claim 2 wherein the MOSFET is coupled to always remain in an off-state with a gate, a source and a body of the MOSFET tied to the ground reference voltage.

5. The apparatus of claim 1 wherein the first and second transistors have breakdown voltages substantially higher than breakdown voltages of other transistors included in the substrate.

6. The apparatus of claim 1 further comprising a power transistor having a first, a second and a third terminal, the first terminal of the power transistor coupled to the first terminals of the first and second transistors, the second terminal of the power transistor coupled to the second terminal of the first transistor, and the third terminal to be coupled to control circuitry.

7. The apparatus of claim 6 wherein the first and second transistors have breakdown voltages substantially higher a breakdown voltage of the power transistor such that any avalanche condition that occurs is to be handled by the power transistor.