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Input queue packet switch architecture and queue service discipline

  • US 20060098673A1
  • Filed: 11/09/2004
  • Published: 05/11/2006
  • Est. Priority Date: 11/09/2004
  • Status: Abandoned Application
First Claim
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1. A packet switching node for switching packets received via a plurality of input ports to a plurality of output ports, the packet switching node comprising:

  • a. a plurality of input queues for queuing packets received at the packet switching node;

    b. at least two head-of-line registers per input queue, each head-of-line register referencing a corresponding head-of-line packet queued in the corresponding input queue; and

    c. inspection means for inspecting the at least two head-of-line packets referenced by the at least two head-of-line registers in selecting a packet for transmission over a corresponding idle destination output port.

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