Method and apparatus for rapid inline measurement of parameter spreads and defects in integrated circuit chips

• US 20060100811A1
• Filed: 10/20/2004
• Published: 05/11/2006
• Est. Priority Date: 10/20/2004
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ketchen, Mark B., Bhushan, Manjul
• Granted Patent: US 7,085,658 B2
• Time in Patent Office: Days
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

A method and apparatus for monitoring a plurality of semiconductor devices is disclosed. At least one array of 2ⁿ semiconductor circuits is provided. A clock ring oscillator provides a clock signal. The clock signal drives a frequency divider followed by an n-stage binary counter. The outputs from the counter'"'"'s stages drive an n-input decoder which sequentially addresses each semiconductor circuit. An output signal from each semiconductor circuit is measured and read out over a common bus, where a distribution of the output signals is a measure of a distribution of a parameter of interest.

Claims

1. A method for monitoring a plurality of semiconductor circuits, comprising:

providing at least one array of semiconductor circuits;

sequentially addressing each semiconductor circuit; and

measuring an output signal from each of said semiconductor circuits, where a distribution of said output signals is a measure of a distribution of a parameter of interest.

2. The method of claim 1, wherein the output signal from each of said semiconductor circuits comprises a voltage.

3. The method of claim 1, wherein the output signal from each of said semiconductor circuits comprises a current.

4. The method of claim 1, wherein the output signal from each of said semiconductor circuits comprises a frequency.

5. The method of claim 1, wherein the parameter of interest comprises a threshold voltage of said semiconductor circuit.

6. The method of claim 1, wherein the parameter of interest comprises a drain current of said semiconductor circuit.

7. The method of claim 1, wherein the parameter of interest comprises a current in a linear region of said semiconductor circuit, where said semiconductor circuit is a transistor.

8. The method of claim 1, wherein the parameter of interest comprises a resistance of said semiconductor circuit.

9. The method of claim 1, wherein said array of semiconductor circuits are sequentially addressed by a decoder.

10. The method of claim 9, wherein said decoder is a one dimensional decoder with one selecting output or a two dimensional decoder with a first selecting output and a second selecting output.

11. The method of claim 9, further comprising:

providing a plurality of clocked input signals to the decoder that are generated by a counter driven by an oscillator circuit.

12. The method of claim 11, wherein the oscillator circuit comprises a ring oscillator and a frequency divider.

13. The method of claim 1, wherein the output signal from each of said semiconductor circuits is multiplexed together to form a continuous output signal with successive increments in time corresponding to successively addressed semiconductor circuits.

14. The method of claim 13, wherein a marker is incorporated in the continuous output signal for identifying a particular time increment with a particular physical location in said at least one array of semiconductor circuits.

15. The method of claim 14, wherein the marker allows identification of each time increment in the output signal with a particular semiconductor circuit.

16. The method of claim 14, wherein said marker is created by omitting one of the said semiconductor circuits such that its output signal is at a zero level.

17. The method of claim 1, wherein said at least one array of semiconductor circuits comprises a plurality of individually addressable semiconductor circuits powered in parallel or in series.

18. The method of claim 17, wherein the semiconductor circuits comprise ring oscillators and the output signal from a selected semiconductor circuit comprises a constant frequency oscillation or a constant current.

19. The method of claim 17, wherein the parameter of interest comprises at least one of a threshold voltage, a via resistance, a wire capacitance and a wire resistance.

20. The method of claim 18, wherein the output of each ring oscillator is used to detect an open or a short.

21. The method of claim 1, wherein the semiconductor circuits comprise n-channel field effect transistors or p-channel field effect transistors and the output signal comprises a current.

22. The method of claim 21, wherein the parameter of interest comprises a drain to source current of the addressed field effect transistor.

23. The method of claim 1, wherein the plurality of semiconductor circuits comprise resistive elements.

24. The method of claim 23, wherein the parameter of interest comprises a resistance of the resistive elements.

25. The method of claim 24, wherein the resistive elements comprise vias, segments of wire, segments of polysilicon or segments of diffusion.

26. An apparatus for monitoring a plurality of semiconductor circuits, comprising:

at least one array of 2ⁿ semiconductor circuits;

a clock ring oscillator having a predefined period for providing a clock signal;

a frequency divider for dividing said clock;

an n-stage binary counter for generating n decoder inputs from said divided clock signal;

a decoder for sequentially addressing each semiconductor circuit using said n decoder inputs; and

a common output bus where a distribution of output signals from said at least one array of semiconductor circuits is a measure of a distribution of a parameter of interest.

27. The apparatus of claim 26, wherein each semiconductor circuit of said at least one array outputs a voltage.

28. The apparatus of claim 26, wherein each semiconductor circuit of said at least one array outputs a current.

29. The apparatus of claim 26, wherein each semiconductor circuit of said at least one array outputs a frequency.

30. The apparatus of claim 26, wherein the parameter of interest comprises a threshold voltage of said semiconductor circuit.

31. The apparatus of claim 26, wherein the parameter of interest comprises a drain current of said semiconductor circuit.

32. The apparatus of claim 26, wherein the parameter of interest comprises a current in a linear region of said semiconductor circuit, where said semiconductor circuit is a transistor.

33. The apparatus of claim 26, wherein the parameter of interest comprises a resistance of said semiconductor circuit.

34. The apparatus of claim 26, wherein the semiconductor circuits comprise ring oscillators.

35. The apparatus of claim 26, wherein the semiconductor circuits comprise n-channel or p-channel field effect transistors.

36. The apparatus of claim 26, wherein said decoder is a one dimensional decoder with one selecting output or a two dimensional decoder with a first selecting output and a second selecting output.

37. The apparatus of claim 26, wherein the output signal from each of said semiconductor circuits is multiplexed together to form a continuous output signal with successive increments in time corresponding to successively addressed semiconductor circuits.

38. The apparatus of claim 37, wherein a marker is incorporated in the continuous output signal for identifying a particular time increment with a particular physical location in said at least one array of semiconductor circuits.

39. The apparatus of claim 38, wherein the marker allows identification of each time increment in the output signal with a particular semiconductor circuit.

40. The apparatus of claim 38, wherein said marker is created by omitting one of the said semiconductor circuits such that its output signal is at a zero level.

41. The apparatus of claim 26, wherein said at least one array of semiconductor circuits comprises a plurality of individually addressable semiconductor circuits powered in parallel or in series.

42. The apparatus of claim 41, wherein the semiconductor circuits comprise ring oscillators and the output signal from a selected semiconductor circuit comprises a constant frequency oscillation or a constant current.

43. The apparatus of claim 41, wherein the parameter of interest comprises at least one of a threshold voltage, a via resistance, a wire capacitance and a wire resistance.

44. The apparatus of claim 42, wherein the output of each ring oscillator is used to detect an open or a short.

45. The apparatus of claim 26, wherein the semiconductor circuits comprise n-channel field effect transistors or p-channel field effect transistors and the output signal comprises a current.

46. The apparatus of claim 45, wherein the parameter of interest comprises a drain to source current of the addressed field effect transistor.

47. The apparatus of claim 26, wherein the plurality of semiconductor circuits comprise resistive elements.

48. The apparatus of claim 47, wherein the parameter of interest comprises a resistance of the resistive elements.

49. The apparatus of claim 48, wherein the resistive elements comprise vias, segments of wire, segments of polysilicon or segments of diffusion.

50. A computer-readable medium having stored thereon a plurality of instructions, the plurality of instructions including instructions which, when executed by a processor, cause the processor to perform the steps of a method for monitoring at least one array of semiconductor circuits comprising:

sequentially addressing each semiconductor circuit; and

measuring an output signal from each of said semiconductor circuits, where a distribution of said output signals is a measure of a distribution of a parameter of interest.

51. The computer-readable medium of claim 50, wherein the output signal from each of said semiconductor circuits comprises a voltage.

52. The computer-readable medium of claim 50, wherein the output signal from each of said semiconductor circuits comprises a current.

53. The computer-readable medium of claim 50, wherein the output signal from each of said semiconductor circuits comprises a frequency.

54. The computer-readable medium of claim 50, wherein the parameter of interest comprises a threshold voltage of said semiconductor circuit.

55. The computer-readable medium of claim 50, wherein the parameter of interest comprises a drain current of said semiconductor circuit.

56. The computer-readable medium of claim 50, wherein the parameter of interest comprises a current in a linear region of said semiconductor circuit, where said semiconductor circuit is a transistor.

57. The computer-readable medium of claim 50, wherein the parameter of interest comprises a resistance of said semiconductor circuit.

58. The computer-readable medium of claim 50, wherein said array of semiconductor circuits are sequentially addressed by a decoder.

59. The computer-readable medium of claim 58, wherein said decoder is a one dimensional decoder with one selecting output or a two dimensional decoder with a first selecting output and a second selecting output.

60. The computer-readable medium of claim 58, further comprising:

providing a plurality of clocked input signals to the decoder that are generated by a counter driven by an oscillator circuit.

61. The computer-readable medium of claim 60, wherein the oscillator circuit comprises a ring oscillator and a frequency divider.

62. The computer-readable medium of claim 50, wherein the output signal from each of said semiconductor circuits is multiplexed together to form a continuous output signal with successive increments in time corresponding to successively addressed semiconductor circuits.

63. The computer-readable medium of claim 62, wherein a marker is incorporated in the continuous output signal for identifying a particular time increment with a particular physical location in said at least one array of semiconductor circuits.

64. The computer-readable medium of claim 63, wherein the marker allows identification of each time increment in the output signal with a particular semiconductor circuit.

65. The computer-readable medium of claim 63, wherein said marker is created by omitting one of the said semiconductor circuits such that its output signal is at a zero level.

66. The computer-readable medium of claim 50, wherein said at least one array of semiconductor circuits comprises a plurality of individually addressable semiconductor circuits powered in parallel or in series.

67. The computer-readable medium of claim 66, wherein the semiconductor circuits comprise ring oscillators and the output signal from a selected semiconductor circuit comprises a constant frequency oscillation or a constant current.

68. The computer-readable medium of claim 66, wherein the parameter of interest comprises at least one of a threshold voltage, a via resistance, a wire capacitance and a wire resistance.

69. The computer-readable medium of claim 67, wherein the output of each ring oscillator is used to detect an open or a short.

70. The computer-readable medium of claim 50, wherein the semiconductor circuits comprise n-channel field effect transistors or p-channel field effect transistors and the output signal comprises a current.

71. The computer-readable medium of claim 70, wherein the parameter of interest comprises a drain to source current of the addressed field effect transistor.

72. The computer-readable medium of claim 50, wherein the plurality of semiconductor circuits comprise resistive elements.

73. The computer-readable medium of claim 72, wherein the parameter of interest comprises a resistance of the resistive elements.

74. The computer-readable medium of claim 73, wherein the resistive elements comprise vias, segments of wire, segments of polysilicon or segments of diffusion.