Automated processor generation system for designing a configurable processor and method for the same

• US 20060101369A1
• Filed: 11/16/2005
• Published: 05/11/2006
• Est. Priority Date: 02/17/2000
• Status: Active Grant

• Current Assignee: Akilesh Parameswar, Albert Ren-Rui Wang, Christopher Mark Songer, David William Goodwin, Dror E. Maydan, Earl A. Killian, Marines Puig Medina, Nupur Bhattacharyya, Pavlos Konas, Rangarajan Srinivasan, Ricardo E. Gonzalez, Richard Ruddell, Walter David Lichtenstein
• Original Assignee: Akilesh Parameswar, Albert Ren-Rui Wang, Christopher Mark Songer, David William Goodwin, Dror E. Maydan, Earl A. Killian, Marines Puig Medina, Nupur Bhattacharyya, Pavlos Konas, Rangarajan Srinivasan, Ricardo E. Gonzalez, Richard Ruddell, Walter David Lichtenstein
• Inventors: Killian, Earl A., Wang, Albert Ren-Rui, Goodwin, David William, Gonzalez, Ricardo E., Parameswar, Akilesh, Konas, Pavlos, Srinivasan, Rangarajan, Bhattacharyya, Nupur, Medina, Marines Puig, Lichtenstein, Walter David, Songer, Christopher Mark, Ruddell, Richard, Maydan, Dror E.
• Granted Patent: US 7,437,700 B2
• Time in Patent Office: Days
• US Class Current: 716/104
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants

Abstract

A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Claims

1. A system for designing a configurable processor, the system comprising:

hardware generation means for, based on a configuration specification including a predetermined portion and a user-defined portion, generating a description of a hardware implementation of the processor; and

software generation means for, based on the configuration specification, generating software development tools specific to the hardware implementation;

wherein the configuration specification includes a statement specifying scheduling information of instructions used in the software development tools;

the hardware generation means is for, based on the statement in the configuration specification, determining whether and how to generate a description of at least one of pipeline logic, pipeline stalling logic and instruction rescheduling logic.

2. The system of claim 1, wherein the scheduling information includes a statement that an operand of an instruction enters a pipeline of the processor at a given stage.

3. The system of claim 1, wherein the scheduling information includes a statement that an operation of an instruction exits a pipeline of the processor at a given stage.

4. The system of claim 1, wherein:

the software generated by the software generation means includes a compiler which uses instructions described in the user-defined portion of the configuration specification; and

the compiler uses the scheduling information during instruction scheduling to schedule the instructions described in the user-defined portion of the configuration specification.

5. The system of claim 1, wherein the configuration specification includes a description of an instruction which requires a plurality of processor cycles to be processed.

6. The system of claim 5, wherein:

the configuration specification includes a description of an instruction'"'"'s semantics which is independent of a target pipeline of the processor; and

the hardware generation means is for generating as part of the processor hardware implementation a pipeline based on a pipeline description separate from the instruction semantics.

7. A system for designing a configurable processor, the system comprising:

hardware generation means for, based on a configuration specification including a predetermined portion and a user-defined portion, generating a description of a hardware implementation of the processor;

software generation means for, based on the configuration specification, generating software development tools specific to the hardware implementation; and

document generation means for generating documentation of a processor instruction set described by the configuration specification based on the configuration specification.

8. The system of claim 7, wherein the document generation means is for using reference semantics of instructions defined in the configuration specification to generate the processor instruction set documentation.

9. The system of claim 7, wherein:

the user-defined portion of the configuration specification contains reference semantics of an instruction defined therein and a user-defined specification of at least one of a synopsis and a text description for the user-defined instruction; and

the document generation means is for using the at least one of the synopsis and the text description to generate documentation of the processor instruction set.

10. A system for designing a configurable processor, the system comprising:

hardware generation means for, based on a configuration specification including a predetermined portion and a user-defined portion, generating a description of a hardware implementation of the processor; and

software generation means for, based on the configuration specification, generating software development tools specific to the hardware implementation;

wherein the user-defined portion of the configuration specification includes a user-defined specification of a processor exception and when a processor instruction raises the exception; and

the hardware generation means includes user-defined exception support generating means for generating hardware supporting that user-defined exception as part of the processor hardware implementation.