Thin film transistor array panel and method for manufacturing the same

• US 20060102907A1
• Filed: 09/16/2005
• Published: 05/18/2006
• Est. Priority Date: 11/17/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Je-Hun, Jeong, Chang-Oh, Cho, Beom-Seok, Bae, Yang-Ho
• Granted Patent: US 7,619,254 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

Claims

1. A thin film transistor array panel comprising:

an insulating substrate;

a gate line formed on the insulating substrate;

a gate insulating layer formed on the gate line;

a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and

a pixel electrode coupled to the drain electrode,

wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

2. The thin film transistor array panel of claim 1, wherein the first conductive layer comprises at least one of ITO, ITON, IZO, and IZON.

3. The thin film transistor array panel of claim 2, wherein the first conductive layer is in an amorphous state.

4. The thin film transistor array panel of claim 1, wherein the first conductive layer is disposed on at least one side of a lower or upper side of the second conductive layer.

5. The thin film transistor array panel of claim 1, wherein the second conductive layer is thicker than the first conductive layer.

6. A manufacturing method of a thin film transistor array panel comprising:

forming a gate line having a gate electrode on an insulating substrate;

depositing a gate insulating layer and a semiconductor layer on the gate line in sequence;

forming a drain electrode and a data line having a source electrode on the gate insulating layer and the semiconductor layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and

forming a pixel electrode coupled to the drain electrode,

wherein at least one of the formation of the gate line and the formation of the data line and drain electrode comprises forming a conductive oxide layer and forming a conductive layer comprising Cu.

7. The method of claim 6, wherein at least one of the formation of the gate line and the formation of the data line and drain electrode comprises a step of forming the conductive oxide layer after forming the conductive layer comprising Cu.

8. The method of claim 6, wherein the conductive oxide layer comprises IZO or ITO.

9. The method of claim 6, wherein the formation of the conductive oxide layer comprises exposing the conductive oxide layer to a nitrogen-containing gas.

10. The method of claim 9, wherein the nitrogen-containing gas is at least one selected from nitrogen gas (N₂), nitrous oxide (N₂O), and ammonia (NH₃).

11. The method of claim 6, wherein the formation of the conductive oxide layer comprises exposing a conductive oxide material for the conductive oxide layer to at least one of hydrogen (H₂) and water vapor (H₂O).

12. The method of claim 6, wherein the formation of the conductive oxide layer is performed at a temperature between 25°

C. to 150°

C.

13. The method of claim 6, wherein at least one of the formation of the gate line and the formation of the data line and drain electrode comprises etching the conductive oxide layer and the conductive layer using a single etchant.

14. The method of claim 7, wherein the conductive oxide layer comprises IZO or ITO.

15. The method of claim 7, wherein the formation of the conductive oxide layer comprises exposing the conductive oxide layer to a nitrogen-containing gas.

16. The method of claim 15, wherein the nitrogen-containing gas is at least one selected from nitrogen gas (N₂), nitrous oxide (N₂O), and ammonia (NH₃).

17. The method of claim 7, wherein the formation of the conductive oxide layer comprises exposing a conductive oxide material for the conductive oxide layer to at least one of hydrogen (H₂) and water vapor (H₂O).

18. The method of claim 7, wherein the formation of the conductive oxide layer is performed at a temperature between 25°

C. to 150°

C.

19. The method of claim 7, wherein at least one of the formation of the gate line and the formation of the data line and drain electrode comprises etching the conductive oxide layer and the conductive layer using a single etchant.