Semiconductor integrated circuit device

• US 20060102934A1
• Filed: 12/30/2005
• Published: 05/18/2006
• Est. Priority Date: 11/13/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hiroyuki Mizuno, Naohiko Irie, Yusuke Kanno
• Inventors: Kanno, Yusuke, Mizuno, Hiroyuki, Irie, Naohiko
• Granted Patent: US 7,217,963 B2
• Time in Patent Office: Days
• US Class Current: 257/204
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors

Abstract

In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Claims

1. A semiconductor integrated circuit device comprising plural flip-flops, plural logic circuits connected to output nodes of the plural flip-flops and first, second and third power lines, wherein:

the flip-flops each comprise a first latch circuit including an output node which is connected with the output node of the flip-flop and a second latch circuit including an input node which is connected with the output node or an input node of the first latch circuit,

an operation voltage for the first latch circuit and the logic circuit is supplied from the first and the second power lines,

an operation voltage for the second latch circuit is supplied from the first and the third power lines,

the first and the second power lines each have a first wiring resistance,

the third power line has a second wiring resistance,

a wiring for connecting the input node of the second latch circuit and the output node or input node of the first latch circuit has a third wiring resistance, and

a difference between the first wiring resistance and the second wiring resistance is smaller than a difference between the second wiring resistance and the third wiring resistance.

2. The semiconductor integrated circuit device according to claim 1, wherein:

the semiconductor integrated circuit device has a first mode and a second mode,

an operation voltage for the logic circuit and the flip-flops is supplied in the first mode,

supply of the operation voltage for the logic circuit and the flip-flop is supplied in the first mode, and

supply of the operation voltage to the logic circuit and the first latch circuit of the flip-flops is stopped, and the supply of the operation voltage for the second latch circuit of the flip-flops is continued in the second mode.

3. The semiconductor integrated circuit device according to claim 2, wherein:

a first MISFET having a source-drain path is provided between the first power line and the third power line, and

the first MISFET is controlled to an ON state in the first mode and the first MISFET is controlled to an OFF state in the second mode.

4. The semiconductor integrated circuit device according to claim 3, wherein:

the first latch circuit and the logic circuit include a second MISFET,

the second latch circuit includes a third MISFET, and

an absolute value for a threshold voltage of the third MISFET is larger than an absolute value for a threshold voltage of the second MISFET.

5. The semiconductor integrated circuit device according to claim 4, wherein:

an absolute value for a threshold voltage of the first MISFET is larger than the threshold voltage of the third MISFET.

6. The semiconductor integrated circuit device according to claim 2, wherein:

a fourth MISFET is provided for connecting the second latch circuit with the second power line, and

the fourth MISFET is turned ON in the first mode and the fourth MISFET is turned OFF in the second mode.

7. The semiconductor integrated circuit device according to claim 6, wherein:

a fifth MISFET is provided for connecting the second latch circuit with the third power line, and

the fifth MISFET is turned OFF in the first mode and the fifth MISFET is turned ON in the second mode.

8. The semiconductor integrated circuit device according to claim 1, wherein:

the operation voltage supplied to the second latch circuit in the second mode is made lower than the operation voltage supplied to the second latch circuit in the first mode.

9. The semiconductor integrated circuit device according to claim 1, wherein:

the second latch circuit has a capacitive element.

10. A semiconductor integrated circuit device comprising:

a first well of a first conductivity type extending in a first direction,

a second well of a second conductivity type disposed adjacent with the first well and extending in the first direction,

a first power line, disposed at an upper layer for the first well, extending in the first direction, for supplying a first potential,

a second power line, disposed at an upper layer for the second well, extending in the first direction and disposed in a layer identical with the first power line, for supplying a second potential,

a first CMOS circuit including a first MISFET of a second conductivity type formed at the first well and a second MISFET of a first conductivity type formed at the second well, and

a second CMOS circuit including a third MISFET of a second conductivity type formed at the first well and a fourth MISFET of a first conductivity type formed at the second well, in which;

a source potential for the first MISFET of the first CMOS circuit is supplied by the first power line, and a source potential for the second MISFET of the first CMOS circuit is supplied by the second power line,

a source potential for the third MISFET of the second CMOS circuit is supplied by the first power line, and a source potential for the fourth MISFET is supplied by the third power line, and

the third power line is present in the layer identical with or below the first power line and the second power line, and has a portion in which a difference between a resistance thereof and a resistance of the first power line or the second power line is smaller than a difference of a resistance between the first power line and the second power line.

11. The semiconductor integrated circuit device according to claim 10, wherein:

plural first power reinforcing lines are provided which are connected with the first power line and which extend in a second direction crossing the first direction,

the first MISFET to fourth MISFET are arranged between adjacent first power reinforcing lines among the plural first power reinforcing lines, and

the third power line has a portion extending in the second direction.

12. The semiconductor integrated circuit device according to claim 10, wherein:

plural second power reinforcing lines are provided which are connected with the second power line and which extend in the second direction crossing the first direction,

the first MISFET to fourth MISFET are arranged between adjacent second power reinforcing lines among the plural second power reinforcing lines, and

the third power line has a portion extending in the second direction.

13. The semiconductor integrated circuit device according to claim 10, wherein:

the third power line is disposed in parallel with the first power line and the second power line.

14. The semiconductor integrated circuit device according to claim 10, wherein:

the semiconductor integrated circuit device comprises plural flip-flops and plural logic circuits connected to output nodes of the plural flip-flops,

the flip-flops each have a first latch circuit including an output node which is connected with the output node of the flip-flop, and a second latch circuit including an input node which is connected with the output node or an input node of the first latch circuit,

the first latch circuit and the logic circuit are comprised of the first CMOS circuit, and

the second latch circuit is comprised of the second CMOS circuit.

15. The semiconductor integrated circuit device according to claim 10, wherein:

an absolute value for a threshold voltage of the third MISFET is larger than an absolute value for a threshold voltage of the first MISFET, and

an absolute value for a threshold voltage of the fourth MISFET is larger than an absolute value for a threshold voltage of the second MISFET.

16. A semiconductor integrated circuit device comprising a logic circuit block having plural flip-flops and plural logic circuits connected with the plural flip-flops and having a first operation mode and a second operation mode, and a clock generation circuit for generating clock signals to be supplied to the logic circuit block, in which the flip-flops each comprise:

a first latch circuit including an output node which is connected with an output node of the flip-flop,

a second latch circuit including an input node which is connected with an input node or the output node of the first latch circuit and

a transfer gate disposed between an input node of the flip-flop and the input node of the first latch circuit,

wherein a first operation voltage is supplied to the first latch circuit and the logic circuit and a second operation voltage is supplied to the second latch circuit,

wherein the clock generation circuit supplies clock signals to the transfer gate in the first operation mode,

wherein, when supply of the first operation voltage to the first latch circuit and the logic circuit is stopped, the second operation voltage is supplied to the second latch circuit and the clock generation circuit stops supply of the clock signal to the transfer gate in the second operation mode,

wherein the transfer gate is turned off for a predetermined period upon transition from the second operation mode to the first operation mode, after the first operation voltage for the first latch circuit of the flip-flop arrives at a predetermined level, and before starting the supply of the clock signal to the transfer gate,

wherein data of the second latch circuit is written back to the first latch circuit for the predetermined period of time,

wherein the first operation voltage is supplied from the first and second power lines,

wherein the second operation voltage is supplied from the first power line and the third power line,

wherein the first power line has a first wiring resistance,

wherein the second power line has a second wiring resistance,

wherein the third power line has a third wiring resistance, and

wherein a difference between the first wiring resistance and the third wiring resistance is smaller than a difference between the first wiring resistance and the second wiring resistance.

17. The semiconductor integrated circuit device according to claim 16, wherein:

a clock inverter supplied with the second operation power is provided between the node of the first latch circuit and the input node of the second latch circuit, and

the clocked inverter is shut off in the second operation mode.

18. The semiconductor integrated circuit device according to claim 16, wherein:

an amount of current supplied to the second latch circuit in the first mode is controlled to be larger than an amount of current supplied to the second latch circuit in the second mode.

19. The semiconductor integrated circuit device according to claim 16, wherein:

the second operation voltage in the second mode is made lower than the second operation voltage in the first mode.

20. The semiconductor integrated circuit device according to claim 16, wherein

the second latch circuit has a capacitance element.

21. The semiconductor integrated circuit device according to claim 16, wherein:

the first latch circuit and the logic circuit include a first MISFET,

the second latch circuit includes a second MISFET, and

an absolute value for a threshold voltage of the second MISFET is larger than an absolute value for a threshold voltage of the first MISFET.

22. The semiconductor integrated circuit device according to claim 16, wherein:

a wiring for connecting the input node or the output node of the first latch circuit with the input node of the second latch circuit has a fourth wiring resistance, and

the difference between the first wiring resistance or the second wiring resistance and the third wiring resistance is smaller than a difference between the fourth wiring resistance and the third wiring resistance.