HYPER THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM

• US 20060103008A1
• Filed: 09/24/2005
• Published: 05/18/2006
• Est. Priority Date: 11/15/2004
• Status: Abandoned Application

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Ong, You Yang, Zukiffly, Zurina binti, Embong, Saat Shukri bin
• Application Number:
  US11/162,828
• Publication Number:
  US 20060103008A1
• Time in Patent Office: Days
• US Class Current: 257/706
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A semiconductor package system is provided including mounting a semiconductor chip to a substrate having a substrate opening. A first heat slug is attached to a first surface of the semiconductor chip at least partially encapsulating the semiconductor chip. A second heat slug is attached to the second surface of the semiconductor chip through the substrate opening.

Claims

1. A semiconductor package system comprising:

mounting a semiconductor chip to a substrate having a substrate opening;

attaching a first heat slug to a first surface of the semiconductor chip, the first heat slug at least partially encapsulating the semiconductor chip; and

attaching a second heat slug to a second surface of the semiconductor chip through the substrate opening.

2. The system as claimed in claim 1 wherein:

mounting the semiconductor chip further comprises reflow soldering stud bumps on the semiconductor chip to solder pillars/ball bumps on the substrate.

3. The system as claimed in claim 1 further comprising:

hermetically sealing the first heat slug to the substrate using a vacuum.

4. The system as claimed in claim 1 wherein:

attaching the first heat slug further comprises providing the first heat slug with a top recess on a top surface thereof;

or

attaching the second heat slug further comprises providing the second heat slug with a bottom recess on a bottom surface thereof.

5. The system as claimed in claim 1 wherein:

attaching the first heat slug further comprises providing the first heat slug with a first fin on a top surface thereof;

or

attaching the second heat slug further comprises providing the first heat slug with a second fin on a bottom surface thereof.

6. A semiconductor package system comprising:

mounting a semiconductor chip by flipping and electrically connecting former top bonding pads to a substrate having a substrate opening;

attaching a top heat slug to a first surface of the semiconductor chip using a conductive bond, the top heat slug at least partially encapsulating the semiconductor chip; and

attaching a bottom heat slug using a conductive bond to a second surface of the semiconductor chip through the substrate opening.

7. The system as claimed in claim 6 wherein:

mounting the semiconductor chip further comprises reflow soldering stud bumps on the semiconductor chip to solder pillars/ball bumps on the substrate;

attaching the top heat slug further comprises attaching the top heat slug with a non-conductive bond to the top of the substrate; and

attaching the bottom heat slug further comprises attaching the bottom heat slug with a non-conductive bond to the bottom of the substrate.

8. The system as claimed in claim 6 further comprising:

hermetically sealing the top heat slug to the substrate using a vacuum suction through the substrate opening.

9. The system as claimed in claim 6 wherein:

attaching the top heat slug further comprises providing the top heat slug with a top recess in the center of a top surface thereof;

attaching the bottom heat slug further comprises providing the bottom heat slug with a bottom recess in the center of a bottom surface thereof;

or

attaching the bottom heat slug further comprises attaching the bottom heat slug in a recessed cavity in the substrate.

10. The system as claimed in claim 6 wherein:

attaching the top heat slug further comprises providing the top heat slug with a first plurality of fins on a top surface thereof;

attaching the bottom heat slug further comprises providing the bottom heat slug with a second plurality of fins on a bottom surface thereof;

or

further comprising attaching a ball grid array on the bottom of the substrate electrically connected to the semiconductor chip.

11. A semiconductor package system comprising:

a semiconductor chip;

a substrate having a substrate opening, the substrate having the semiconductor chip mounted thereon;

a first heat slug attached to a first surface of the semiconductor chip, the first heat slug at least partially encapsulating the semiconductor chip; and

a second heat slug attached to a second surface of the semiconductor chip through the substrate opening.

12. The system as claimed in claim 11 wherein:

the substrate further comprises solder pillars/ball bumps; and

the semiconductor chip further comprises stud bumps for conductively connecting the semiconductor chip to the solder pillars/ball bumps on the substrate.

13. The system as claimed in claim 11 wherein:

the substrate further comprises a vertical built-up wing; and

a solder mask on the substrate within the vertical built-up wing.

15. The system as claimed in claim 11 wherein:

the first heat slug further comprises a first fin on a top surface thereof;

or

the second heat slug further comprises a second fin on a bottom surface thereof.

14. The system as claimed in claim 111 wherein:

the first heat slug further comprises a top recess on a top surface thereof;

the second heat slug further comprises a bottom recess on a bottom surface thereof;

or

the first and second heat slugs provide at least 80% of the surface area of the semiconductor package system.

16. A semiconductor package system comprising:

a semiconductor chip;

a substrate having a substrate opening, the substrate having the semiconductor chip flipped and electrically mounted thereon;

a top heat slug to a first surface of the semiconductor chip using a conductive adhesive, the top heat slug at least partially encapsulating the semiconductor chip; and

a bottom heat slug using a conductive adhesive to a second surface of the semiconductor chip through the substrate opening.

17. The system as claimed in claim 16 wherein:

the semiconductor chip further comprises stud bumps on the semiconductor chip electrically connected to solder pillars/ball bumps on the substrate;

the top heat slug further comprises a non-conductive adhesive attaching the top heat slug to the top of the substrate; and

the bottom heat slug further comprises a non-conductive adhesive attaching the bottom heat slug to the bottom of the substrate.

18. The system as claimed in claim 16 wherein:

the substrate further comprises a vertical built-up wing; and

further comprising;

a solder mask on the substrate within the vertical built-up wing; and

solder pillars/ball bumps on the substrate in openings in the solder mask.

19. The system as claimed in claim 16 wherein:

the top heat slug further comprises a top recess in the center of a top surface thereof;

the bottom heat slug further comprises a bottom recess in the center of a bottom surface thereof;

the bottom heat slug further comprises the bottom heat slug in a recessed cavity in the substrate;

or

the first and second heat slugs provide at least 85% of the surface area of the semiconductor package system.

20. The system as claimed in claim 16 wherein:

the top heat slug further comprises a first plurality of fins on a top surface thereof;

the bottom heat slug further comprises a second plurality of fins on a bottom surface thereof;

or

further comprising a ball grid array on the bottom of the substrate electrically connected to the semiconductor chip.