Methods for incorporating high k dielectric materials for enhanced SRAM operation and structures produced thereby

• US 20060103023A1
• Filed: 11/12/2004
• Published: 05/18/2006
• Est. Priority Date: 11/12/2004
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Kosonocky, Stephen V., Purushothaman, Sampath, Bhavnagarwala, Azeez J., Nitta, Satyanarayana V.
• Application Number:
  US10/988,484
• Publication Number:
  US 20060103023A1
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip is described. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.

Claims

1. Independent Structure Claim:

An interconnect structure comprising a multitude of conductors disposed atop a first dielectric wherein the spaces between a first subset of said multitude of conductors is occupied by a second dielectric and the spaces between a second subset of said multitude of conductors is occupied by a third dielectric.

2. A structure according to claim 1 wherein said multitude of conductors are interconnect wires comprising a conductive barrier liner and a higher conductivity fill material.

3. A structure according to claim 1 wherein said first dielectric is a mechanically robust dielectric selected from the group comprising silicon oxide, fluorinated silicon oxide, organosilicate dielectrics comprising silicon, carbon, oxygen and hydrogen.

4. A structure according to claim 1 wherein said second dielectric is selected from the group comprising dielectrics deposited by spin coating or plasma enhanced chemical vapor deposition and selected from the group comprising silicon oxide, fluorinated silicon oxide, titania, zirconia, hafnia and their silicates, barium strontium titanate, barium zirconium titanate and the like.

5. A structure according to claim 1 wherein said third dielectric is selected from the group comprising porous and dense versions of organosilicates and organic dielectrics such as polyimides and polyarylene ethers and porous silica.

6. A structure according to claim 1 wherein said first subset of conductors are interconnect wires located within the SRAM portion of a microelectronic chip.

7. A structure according to claim 6 wherein said first subset of conductors comprises the word and power lines of an SRAM cell.

8. A structure according to claim 1 wherein said first dielectric is also disposed in the dicing channels and under bonding and test pads in the chip.

9. A structure according to claim 1 wherein said second subset of conductors are located in regions other than the SRAM cells and serve to interconnect different regions on the chip.

10. A structure according to claim 1 wherein said various dielectrics are deposited using a method selected from spin coating and curing, sol gel processing, chemical vapor deposition, plasma assisted chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

11. The structure according to claim 1 wherein said conductive barrier material is selected from the group comprising tantalum and titanium,nitrides and siliconitrides of tantalum and titanium and combinations thereof.

12. The structure according to claim 1 wherein said higher conductivity filler material is selected from the group comprising copper, aluminum, gold, silver and combinations thereof.

13. The structure according to claim 1 wherein said structure is a mechanically robust microelectronic chip with a high interconnect capacitance in the SRAM regions and low interconnect capacitance in the other interconnect regions.

14. (Independent Claim:

Method 1;

Build in robust IMD, EBGF ULK) A method to fabricate a hybrid interconnect structure comprising the steps of;

depositing a first dielectric and patterning trenches and vias in said first dielectric on a substrate;

filling said trenches and vias with a conductive barrier and a higher conductivity fill material to form interconnect wiring structures;

forming a block out resist pattern in a first region of the substrate to expose only a first subset of said interconnect structures;

etching said first dielectric from between said first set of interconnect wires located in said first region;

and filling the gaps between said first set of interconnect wires with a second dielectric and planarizing it to form a coplanar structure.

15. The method according to claim 14 wherein said first dielectric is selected from the group comprising silicon oxide, fluorinated silicon oxide, organosilicate dielectrics comprising silicon, carbon, oxygen and hydrogen.

16. The method according to claim 14 wherein said conductive barrier material is selected from the group comprising tantalum and titanium, nitrides and siliconitrides of tantalum and titanium and combinations thereof.

17. The method according to claim 14 wherein said higher conductivity fill material is selected from the group comprising copper, aluminum, gold, silver and combinations thereof.

18. The method according to claim 14 wherein said substrate is a microelectronic chip comprising at least logic blocks, SRAM cells, bond and test pads and dicing channels.

19. The method according to claim 18 wherein said first region consists of all the regions other than the SRAM cells, dicing channels and the areas used for bond and test pads.

20. The method according to claim 14 wherein said etching of said first dielectric is achieved by a process selected from plasma etching, reactive ion etching, ion milling, laser etching and wet etching.

21. The method according to claim 14 wherein said second dielectric is selected from the group comprising porous and dense versions of organosilicates and organic dielectrics such as polyimides and polyarylene ethers and porous silica.

22. The method according to claim 14 wherein said planarization of said second dielectric is achieved by chemical mechanical polishing, reactive ion etching or a combination thereof.

23. The method according to claim 14 wherein the steps are repeated to produce a multilevel hybrid interconnect structure.

24. (Method 2:

ULK/LK first and UHK next) The method according to claim 14 wherein said first dielectric is a low k or ultra low k dielectric selected from the group comprising porous and dense versions of organosilicates and organic dielectrics such as polyimides and polyarylene ethers and porous silica.

25. The method according to claim 24 wherein said first region comprises only the SRAM cells on a microelectronic chip.

26. The method according to claim 24 wherein said second dielectric is a high k dielectric selected from the group comprising silicon oxide, fluorinated silicon oxide, titania, zirconia, hafnia and their silicates, barium strontium titanate, barium zirconium titanate and the like.

35. The methods according to claims 14, 24 and 27 wherein said hybrid interconnect structure produced thereby is a mechanically robust microelectronic chip with a high interconnect capacitance in the SRAM regions and low interconnect capacitance in the other interconnect regions.

36. A structure according to claim 1 wherein the higher capacitance in the SRAM cells is utilized to enable higher power supply voltage thereby increasing the static noise margin and reduced leakage in the SRAM cells.

37. A structure according to claim 1 wherein the higher capacitance in the SRAM cells is utilized to enable higher power supply voltage thereby leading to the use of a single power supply voltage for both logic and SRAM regions of a microelectronic chip.

38. A method of modifying an interconnect structure fabricated according to claim 14 by:

protecting all areas other than the SRAM cell area with a block out resist pattern;

treating the exposed SRAM cell region by a method selected from ion implanation, photon irradiation, chemical infiltration from liquid, vapor or supercritical fluid media thermal annealning and combinations thereof;

resulting in the modification of the intermetal dielectric in said SRAM cell area to a higher dielectric constant so as to enable higher capacitive coupling between the interconnect lines in said SRAM cell area;

and stripping the blockout photoresist from the surface.

44. The methods according to claims 14, 24, 27 and 39 that result in a microelectronic chip with a mechanically robust hybrid interconnect structure and operating with a higher static noise margin and reduced leakage SRAM cells.

45. The methods according to claims 14, 24, 27 and 39 that result in a microelectronic chip with a mechanically robust hybrid interconnect structure and capable of operating with a single power supply voltage for both the SRAM and logic cells in said chip.

27. (Method 3:

Build in robust IMD/EBGF UHK/EBGF ULK) A method of fabricating a hybrid interconnect structure comprising the steps of;

depositing a first dielectric and patterning trenches and vias in said first dielectric on a substrate;

filling said trenches and vias with a conductive barrier and a higher conductivity fill material to form interconnect wiring structures;

forming a first block out resist pattern to expose only a first set of interconnects in a first region of the substrate;

etching said first dielectric from between said first set of interconnect wires located in said first region and stripping the photoresist;

filling the etched gaps between said first set of interconnect wires with a second dielectric and planarizing it to form a coplanar structure;

forming a second blockout photoresist pattern that exposes a second region of the substrate comprising a second set of interconnects;

etching said first dielectric from between said second set of interconnects and stripping the photoresist;

and filling the etched gaps between said second set of interconnects with a third dielectric and planarizing to form a coplanar structure.

28. A method according to claim 27 wherein said substrate is a microelectronic chip comprising at least logic blocks, SRAM cells, bond and test pads and dicing channels.

29. A method according to claim 27 wherein said first set of interconnects are locate din the SRAM cell area of said chip.

30. A method according to claim 27 wherein said first dielectric is selected from the group comprising silicon oxide, fluorinated silicon oxide, organosilicate dielectrics comprising silicon, carbon, oxygen and hydrogen.

31. A method according to claim 27 wherein said second dielectric is selected from group comprising titania, zirconia, hafnia and their silicates, barium strontium titanate, barium zirconium titanate and the like.

32. A method according to claim 27 wherein said second region comprises all the chip area except the SRAM cells, dicing channels and the bond and test pads.

33. A method according to claim 27 wherein said third dielectric is selected from the group comprising porous and dense versions of organosilicates and organic dielectrics such as polyimides and polyarylene ethers and porous silica.

39. A method of fabricating a hybrid interconnect structure comprising the steps of:

depositing a first dielectric and patterning trenches and vias in said first dielectric on a substrate;

filling said trenches and vias with a conductive barrier and a higher conductivity fill material to form interconnect wiring structures;

forming a block out resist pattern in a first region of the substrate to expose only a first subset of said interconnect structures;

treating said first subset of said interconnect structures by a method selected from ion implanation, photon irradiation, chemical infiltration from liquid, vapor or supercritical fluid media, thermal annealing and combinations thereof;

resulting in the modification of the said first dielectric in said exposed area to convert it into a second dielectric with a higher dielectric constant so as to enable higher capacitive coupling between the interconnect lines in said exposed region;

and stripping the blockout photoresist from the surface.

40. A method according to claim 39 wherein said first dielectric is selected from the group comprising porous and dense versions of organosilicates and organic dielectrics such as polyimides and polyarylene ethers and porous silica.

41. A method according to claim 39 wherein said conductive barrier material is selected from the group comprising tantalum and titanium, nitrides and siliconitrides of tantalum and titanium and combinations thereof.

42. A method according to claim 39 wherein said higher conductivity fill material is selected from the group comprising copper, aluminum, gold, silver and combinations thereof.

43. A method according to claim 39 wherein said exposed first subset of interconnects are part of the SRAM cell region of a microelectronic chip.