Digital signal demodulator and wireless receiver using the same

• US 20060103561A1
• Filed: 11/08/2005
• Published: 05/18/2006
• Est. Priority Date: 11/10/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nishigaki, Michihiko, Abe, Kazuhide, Kawakubo, Takashi, Nagano, Toshihiko
• Granted Patent: US 7,796,710 B2
• Time in Patent Office: Days
• US Class Current: 341/143
• CPC Class Codes: H04L 27/2276 using frequency multiplication or harmonic tracking

Abstract

A digital demodulator includes a resonator having a resonance frequency same as a carrier frequency to store a charge corresponding to a digital signal modulated by phase shift keying, a capacitor to store the charge of the resonator, an amplifier including an input node and an output node between which the capacitor is connected to convert a stored charge of the capacitor into a voltage signal, and a controller configured to accumulate in the resonator the charge induced by the frequency signal modulated by phase shift keying in a first control mode and configured to transfer the charge of the resonator to the capacitor in a second control mode, to output the voltage signal corresponding to the stored charge of the capacitor from the output node of the amplifier.

Claims

1. A digital demodulator of demodulating a frequency signal modulated by phase shift keying and having a specific carrier frequency, the digital demodulator comprising:

a resonator having a resonance frequency same as a carrier frequency to store a charge corresponding to a digital signal modulated by phase shift keying;

a capacitor to store the charge of the resonator;

an amplifier including an input node and an output node between which the capacitor is connected to convert a stored charge of the capacitor into a voltage signal; and

a controller configured to accumulatein the resonator the charge induced by the frequency signal modulated by phase shift keying in a first control mode and configured to transfer the charge of the resonator to the capacitor in a second control mode, to output the voltage signal corresponding to the stored charge of the capacitor from the output node of the amplifier.

2. The digital demodulator according to claim 1, further comprising a lowpass filter to extract a dc component from the output signal of the amplifier to produce a demodulated output digital signal.

3. The digital demodulator according to claim 1, wherein the controller controls the resonator and the amplifier to store the charge induced by the frequency signal modulated by phase shift keying in the resonator in the first control mode to integrate the frequency signal, and extract a voltage digital signal including a dc component of a polarity corresponding to phase information of the frequency signal modulated by phase shift keying as a voltage digital signal corresponding to the stored charge of the capacitor in the second control mode.

4. The digital demodulator according to claim 1, wherein the controller comprises a first switch connected between a signal input node to which the frequency signal modulated by phase shift keying is input and a first node of the resonator, a second switch connected between a second node of the resonator and a first input node of the amplifier, and a switch control circuit to turn on the first switch and turn off the second switch in the first control mode, and turn off the first switch and turn on the second switch in the second control mode.

5. The digital demodulator according to claim 1, wherein the controller comprises a first switch connected between a signal input node to which the frequency signal modulated by phase shift keying is input and a first node of the resonator, a second switch connected between a second node of the resonator and an input node of the amplifier, a third switch connected between the first node of the resonator and a reference potential node, a fourth switch connected between the second node of the resonator and the reference potential node, a fifth switch connected between both nodes of the capacitor, and a switch control circuit to turn on the first switch, turn off the second switch, turn off the third switch, turn on the fourth switch and turn on the fifth switch, in the first control mode, and turn off the first switch, turn on the second switch, turn on the third switch, turn off the fourth switch and turn off the fifth switch, in the second control mode.

6. The digital demodulator according to claim 1, wherein the resonator comprises a thin film piezoelectric resonator.

7. The digital demodulator according to claim 1, wherein the amplifier comprises a differential amplifier including an inverting input node and a noninverting input node connected to a reference potential point, the second switch is connected between the second node of the resonator and the inverting input node of the differential amplifier, and the capacitor is connected between the inverting input node of the differential amplifier and an output node thereof.

8. The digital demodulator according to claim 1, comprising a demodulation integrated circuit device connectable to the resonator, and including the capacitor, the amplifier and the controller which are integrated.

9. A digital demodulator to demodulate a frequency signal modulated by phase shift keying, comprising:

a plurality of unit demodulators each comprising;

a resonator having a resonance frequency same as a carrier frequency to store a charge corresponding to a frequency signal modulated by phase shift keying;

a capacitor to store the charge of the resonator;

an amplifier including an input node and an output node between which the capacitor is connected to convert a stored charge of the capacitor into a voltage signal; and

a controller configured to accumulate in the resonator the charge induced by the frequency signal modulated by phase shift keying in a first control mode, and configured to transfer the charge of the resonator to the capacitor in a second control mode, to output the voltage signal corresponding to the stored charge of the capacitor from the output node of the amplifier, the controller changing the unit demodulators to the first control mode and the second control mode at a different timing.

10. The digital demodulator according to claim 9, which the unit demodulators comprise two unit demodulators for I and Q channels to demodulate a quadrature phase shift keying (QPSK) signal including digital information represented by 2-bit symbols “

00”

, “

01”

, “

10” and

“

11”

.

11. The digital demodulator according to claim 9, wherein each of the unit demodulators further comprises a lowpass filter to extract a dc component from the output signal of the amplifier to produce a demodulated output signal.

12. A wireless receiver comprising

a receiving unit configured to receive a frequency signal modulated by phase shift keying having a specific carrier frequency;

a digital demodulator of demodulating the frequency signal modulated by phase shift keying, including;

a resonator having a resonance frequency same as a carrier frequency to store a charge corresponding to a frequency signal modulated by phase shift keying;

a capacitor to store the charge of the resonator;

an amplifier including an input node and an output node between which the capacitor is connected to convert a stored charge of the capacitor into a voltage signal; and

a controller configured to accumulate in the resonator the charge induced by the frequency signal modulated by phase shift keying in a first control mode, and configured to transfer the charge of the resonator to the capacitor in a second control mode, to output the voltage signal corresponding to the stored charge of the capacitor from the output node of the amplifier;

an AD converter to convert the voltage signal of the digital demodulator into a digital signal; and

a baseband processor to process the digital signal to reproduce receive data.

13. The wireless receiver according to claim 12, further comprising a lowpass filter to extract a dc component from the output signal of the amplifier to produce a demodulated output signal.

14. The wireless receiver according to claim 12, wherein the controller controls the resonator and the amplifier to store the charge induced by the frequency signal modulated by phase shift keying in the resonator in the first control mode to integrate the frequency signal, and extract a voltage signal including a dc component of a polarity corresponding to phase information of the integrated frequency signal modulated by phase shift keying as a voltage signal corresponding to the stored charge of the capacitor in the second control mode.

15. The wireless receiver according to claim 12, wherein the controller comprises a first switch connected between a signal input node to which the frequency signal is input and a first node of the resonator, a second switch connected between a second node of the resonator and a first input node of the amplifier, and a switch control circuit to turn on the first switch and turn off the second switch in the first control mode, and turn off the first switch and turns on the second switch in the second control mode.

16. The wireless receiver according to claim 12, wherein the controller comprises a first switch connected between a signal input node to which the frequency signal modulated by phase shift keying is input and a first node of the resonator, a second switch connected between a second node of the resonator and an input node of the amplifier, a third switch connected between the first node of the resonator and a reference potential node, a fourth switch connected between the second node of the resonator and the reference potential node, a fifth switch connected between both nodes of the capacitor, and a switch control circuit to turn on the first switch, turn off the second switch, turn off the third switch, turn on the fourth switch and turn on the fifth switch, in the first control mode, and turn off the first switch, turn on the second switch, turn on the third switch, turn off the fourth switch and turn off the fifth switch, in the second control mode.

17. The wireless receiver according to claim 12, wherein the resonator comprises a thin film piezoelectric resonator.

18. The wireless receiver according to claim 12, wherein the amplifier comprises a differential amplifier including an inverting input node and a noninverting input node connected to a reference potential point, the second switch is connected between the second node of the resonator and the inverting input node of the differential amplifier, and the capacitor is connected between the inverting input node of the differential amplifier and an output node thereof.

19. The wireless receiver according to claim 12, which comprises a plurality of unit demodulators each comprising the digital demodulator, and wherein the controller is configured to change the unit demodulators to the first control mode and the second control mode at a different timing.

20. The wireless receiver according to claim 12, which the demodulator comprises two unit demodulators for I and Q channels to demodulate a quadrature phase shift keying (QPSK) signal including digital information represented by 2-bit symbols “

00”

, “

01”

, “

10” and

“

11”

.