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Latency tolerant system for executing video processing operations

  • US 20060103659A1
  • Filed: 11/04/2005
  • Published: 05/18/2006
  • Est. Priority Date: 11/15/2004
  • Status: Active Grant
First Claim
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1. A latency tolerant system for executing video processing operations, comprising:

  • a host interface for implementing communication between the video processor and a host CPU;

    a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations;

    a vector execution unit coupled to the host interface and configured to execute vector video processing operations;

    a command FIFO for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO;

    a memory interface for implementing communication between the video processor and a frame buffer memory; and

    a DMA engine built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading a datastore memory and an instruction cache with data and instructions for the vector execution unit.

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