Latency tolerant system for executing video processing operations
First Claim
1. A latency tolerant system for executing video processing operations, comprising:
- a host interface for implementing communication between the video processor and a host CPU;
a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations;
a vector execution unit coupled to the host interface and configured to execute vector video processing operations;
a command FIFO for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO;
a memory interface for implementing communication between the video processor and a frame buffer memory; and
a DMA engine built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading a datastore memory and an instruction cache with data and instructions for the vector execution unit.
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Abstract
A latency tolerant system for executing video processing operations. The system includes a host interface for implementing communication between the video processor and a host CPU, a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations, and a vector execution unit coupled to the host interface and configured to execute vector video processing operations. A command FIFO is included for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A DMA engine is built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading the command FIFO with data and instructions for the vector execution unit.
237 Citations
20 Claims
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1. A latency tolerant system for executing video processing operations, comprising:
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a host interface for implementing communication between the video processor and a host CPU;
a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations;
a vector execution unit coupled to the host interface and configured to execute vector video processing operations;
a command FIFO for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO;
a memory interface for implementing communication between the video processor and a frame buffer memory; and
a DMA engine built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading a datastore memory and an instruction cache with data and instructions for the vector execution unit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for latency tolerant video processing operations, comprising:
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implementing communication between the video processor and a host CPU by using a host interface;
executing scalar video processing operations by using a scalar execution unit coupled to the host interface;
executing vector video processing operations by using vector execution unit coupled to the host interface;
enabling the vector execution unit to operate on a demand driven basis by accessing a memory command FIFO;
implementing communication between the video processor and a frame buffer memory by using a memory interface; and
implementing DMA transfers between a plurality of different memory locations by using a DMA engine built into the memory interface and configured for loading a datastore memory and an instruction cache with data and instructions for the vector execution unit. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A latency tolerant system for executing video processing operations, comprising:
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a motherboard;
a host CPU coupled to the motherboard;
a video processor coupled to the motherboard and coupled to the CPU, comprising;
a host interface for implementing communication between the video processor and a host CPU;
a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations;
a vector execution unit coupled to the host interface and configured to execute vector video processing operations;
a command FIFO for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO;
a memory interface for implementing communication between the video processor and a frame buffer memory; and
a DMA engine built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading a datastore memory and an instruction cache with data and instructions for the vector execution unit. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification