High Q factor integrated circuit inductor

• US 20060105534A1
• Filed: 12/28/2005
• Published: 05/18/2006
• Est. Priority Date: 01/29/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Stein, Kenneth J., Cotte, John M., Edelstein, Daniel C., Petrarca, Kevin S., Deligianni, Hariklia, Volant, Richard P., Magerlein, John H., Andricacos, Panayotis C.
• Granted Patent: US 7,638,406 B2
• Time in Patent Office: Days
• US Class Current: 438/329
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05007 comprising a core and a coating
• CPC Class Codes: H01L 2224/05014 being square
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05084 Four-layer arrangements
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48644 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48724 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48744 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

An inductor and a method of forming and the inductor, the method including: (a) forming a dielectric layer on a top surface of a substrate; (b) forming a lower trench in the dielectric layer; (c) forming a resist layer on a top surface of the dielectric layer; (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (e) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

Claims

1. A method of forming an inductor, comprising:

(a) forming a dielectric layer on a top surface of a substrate;

after step (a), (b) forming a lower trench in said dielectric layer;

after step (b), (c) forming a resist layer on a top surface of said dielectric layer;

after step (c), (d) forming an upper trench in said resist layer, said upper trench aligned to said lower trench, a bottom of said upper trench open to said lower trench; and

after step (d), (e) completely filling said lower trench and at least partially filling said upper trench with a conductor in order to form said inductor.

2. The method of claim 1, further including:

forming a via in said dielectric layer to an I/O terminal pad in said substrate.

3. The method of claim 2, further including forming a wirebond pad electrically contacting said I/O terminal pad through said via.

4. The method of claim 2, further including forming a solder ball connection contacting said I/O terminal pad through said via.

5. The method of claim 4, wherein said forming said solder ball connection comprises electroplating one or more metals over said I/O terminal pad.

6. The method of claim 1, wherein:

step (b) includes forming a via in said dielectric layer, a bottom of said via open to an I/O terminal pad in said substrate;

step (c) includes forming a trench in said resist layer, said trench aligned to said via and a bottom of said trench in said resist layer open to said via; and

step (e) includes completely filling said via and at least partially filling said trench with said conductor to form a raised contact pad.

7. The method of claim 6, further including forming a solder ball connection contacting said raised contact pad.

8. The method of claim 7, wherein said forming said solder ball connection comprises evaporating one or more metals through a mask aligned to said substrate.

9. The method of claim 7, wherein said forming said solder ball connection comprises electroplating one or more metals over said I/O terminal pad.

10. The method of claim 1, wherein said lower trench is formed a distance into said dielectric layer that is less than a distance between said top surface of said dielectric layer and a bottom surface of said dielectric layer.

11. The method of claim 10, wherein:

step (b) includes forming vias to underpass connection wires in said substrate, said vias formed in a bottom surface of said lower trench; and

step (e) includes completely filling said vias with said conductor.

12. The method of claim 1, further including:

after step e, (f) removing said resist layer and forming a conductive passivation layer over said inductor.

13. The method of claim 1, wherein said upper and lower trenches are spiral trenches.

14. The method of claim 1, wherein said conductor comprises Cu or a TaN/Ta liner and a Cu core.

15. A method of forming an inductor, comprising:

(a) forming a dielectric layer on a top surface of a substrate;

after step (a), (b) forming a lower trench in said dielectric layer;

after step (b), (c) forming a conformal conductive liner in said lower trench and over a top surface of said dielectric layer;

after step (c), (d) forming a conformal Cu seed layer over said conductive liner;

after step (d), (e) forming a resist layer on said substrate;

after step (e), (f) forming an upper trench in said resist layer, said upper trench aligned to said lower trench, a bottom of said upper trench open to said lower trench;

after step (f), (g) electroplating Cu to completely fill said lower trench and at least partially fill said upper trench in order to form said inductor;

after step (g), (h) removing said resist layer;

after step (h), (i) selectively forming a conductive passivation layer over all exposed Cu surfaces; and

after step (i), (j) selectively removing said Cu seed layer from regions of said conductive liner overlying said surface of said dielectric layer and removing said conductive liner from said surface of said dielectric layer.

16. The method of claim 15:

further including after step (d) removing said Cu seed layer from regions of said conductive liner overlying said top surface of said dielectric layer and leaving said seed layer on said conductive liner on sidewalls and a bottom surface of said lower trench; and

wherein step (j) does not include removing said seed layer from said regions of said conductive layer overlying said top surface of said dielectric layer.

17. The method of claim 15, further including:

forming a via in said dielectric layer to an I/O terminal pad in said substrate.

18. The method of claim 17, further including:

forming a via in said dielectric layer, said via aligned to said I/O terminal;

forming a polyimide layer over said substrate, said polyimide layer aligned to said via in said dielectric layer; and

forming a via in said polyimide layer, said via in said polyimide layer aligned to said I/O terminal and defining a wirebond pad.

19. The method of claim 17, further including forming a solder ball connection contacting said I/O terminal pad through said vias in said polyimide layer and said dielectric layer.

20. The method of claim 19, wherein said forming said solder ball connection comprises evaporating or sputtering a pad limiting metallurgy layer and a seed layer and electroplating a Pb layer or a Pb/Sn alloy layer.

21. The method of claim 15, wherein:

step (b) includes forming a via in said dielectric layer to an I/O terminal pad in said substrate;

step (c) includes forming a conformal conductive liner in said via in said dielectric layer;

step (f) includes forming a trench in said resist layer, said trench aligned to said via in said dielectric layer, a bottom of said trench open to said via in said dielectric layer; and

step (h) includes electroplating Cu to completely fill said via in said dielectric layer and at least partially fill said trench to form a raised contact pad.

22. The method of claim 21, further including forming a solder ball connection contacting said raised contact pad.

23. The method of claim 22, wherein said forming said solder ball connection comprises evaporating or sputtering a pad limiting metallurgy layer and a Pb layer or a Pb/Sn alloy layer through a mask aligned to said substrate.

24. The method of claim 22, wherein said forming said solder ball connection comprises sputtering a pad limiting metallurgy layer and a seed layer and electroplating a Pb layer or a Pb/Sn alloy layer.

25. The method of claim 15, wherein said lower trench is formed a distance into said dielectric layer that is less than a distance between said top surface of said dielectric layer and a bottom surface of said dielectric layer.

26. The method of claim 25, wherein:

step (b) includes forming vias to underpass connection wires in said substrate, said vias formed in a bottom surface of said lower trench; and

step (g) includes electroplating Cu to completely fill said vias in said bottom surface of said lower trench.

27. The method of claim 15, wherein said conductive passivation layer comprises a layer of Ni or a layer of Au over a layer of Ni.

28. The method of claim 15, wherein said upper and lower trenches are spiral trenches and said inductor is a spiral inductor.

29. The method of claim 15, wherein said dielectric layer comprises an upper layer of Si₃N₄ in contact with a top surface of an SiO₂ layer, said SiO₂ layer in contact with a top surface of a lower Si₃N₄ layer.

30. The metal of claim 15, wherein step (g) electroplates Cu to a depth of at least 5 microns.