Method for reducing memory size in logarithmic number system arithmetic units

• US 20060106905A1
• Filed: 11/17/2004
• Published: 05/18/2006
• Est. Priority Date: 11/17/2004
• Status: Abandoned Application

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Chren, William A. Jr.
• Application Number:
  US10/990,405
• Publication Number:
  US 20060106905A1
• Time in Patent Office: Days
• US Class Current: 708/270
• CPC Class Codes: G06F 1/0307 Logarithmic or exponential functions G06F1/0314, G06F1/035 take precedence
• CPC Class Codes: G06F 7/4833 Logarithmic number system

Abstract

A method for performing addition/subtraction on logarithmic number system (LNS) operands x and y that uses a single lookup table. The lookup table is populated by values of ln(1+exp(−α)) where α is an absolute value of difference of x and y. To perform an addition operation, the lookup table is accessed a single time and the lookup table output added to the largest of the input operands to produce the result. To perform a subtraction operation the addition lookup table is successively addressed by left-shifted versions of α, the table outputs are accumulated, and accumulated lookup table output added to the largest of the input operands to produce the subtraction result.

Claims

1. A method of computing a mathematical function of logarithmic number system (LNS) operands x and y in a computing device, the method comprising:

populating a lookup table with values;

providing a value a from an absolute value of difference of x and y;

when performing an addition operation, accessing the lookup table a single time using the value α and

adding the lookup table output added to the largest of the input operands to produce the addition result; and

when performing a subtraction operation accessing the lookup table a plurality of times with different versions of the value α

, accumulating the lookup table outputs, and adding the largest of the input operands to the accumulated lookup table outputs to produce the subtraction result.

2. The method of claim 1 wherein the different versions of a are determined by left-shifted versions of α

.

3. The method of claim 1 wherein the different versions of a are multiples of α

.

4. The method of claim 1 wherein the lookup table comprises a plurality of entries indexed by α

and each entry holds a predetermined value ln(1+exp(−

α

)).

5. The method of claim 1 wherein the act of performing a subtraction comprises accessing the lookup table n times using a series [α

, 2α

, 4α

, . . . 2ⁿα

].

6. The method of claim 1 wherein the act of performing a subtraction comprises accessing the lookup table at least nine times each with a different version of α

.

7. The method of claim 1 further comprising:

providing an addition/subtraction select signal;

using the addition/subtraction select signal to selectively couple one of either the lookup table output or the accumulated lookup table output to an adder; and

using the addition/subtraction signal to generate the different versions of the value α

.

8. The method of claim 1 wherein the number of times that the lookup table is accessed when performing a subtraction is selected to satisfy preselected error requirements.

9. A computing device implementing the method of claim 1.

10. A digital signal processor implementing the method of claim 1.

11. A math unit for performing a function on two logarithmic number system (LNS) operands x and y, the math unit comprising:

a component for determining a value α

by finding the absolute value of the difference of two LNS operands x and y;

an address generator coupled to receive α and

generate a plurality of address values from α

;

a lookup table comprising a plurality of entries, wherein a value of a selected entry is output in response to an address identifying the selected entry;

a first selector for selectively coupling either a or the plurality of addresses generated from a to an input of an adder; and

a second selector for selectively coupling the largest of the two LNS operands x and y to an input of the adder, wherein an output of the adder is a LNS result of a function of the two LNS operands.

12. The math unit of claim 11 wherein x and y are LNS representations of floating point values β

₁ and β

₂, respectively and the function implemented by the math unit comprises β

₁±

β

₂ln(exp(ln(β

₁))±

(exp(ln(β

₂)))=ln(exp(x)±

exp(y)).

13. The math unit of claim 11 wherein the lookup table values cumulatively describe a function ln(1+exp(−

α

)).

14. The math unit of claim 11 wherein the math unit is configured to perform an addition by addressing the lookup table a single time using a and adding the lookup table output to the largest of the LNS operands.

15. The math unit of claim 14 wherein the math unit is configured to perform a subtraction by successively addressing the lookup table.

16. The math unit of claim 11 wherein the address generator comprises a shift register coupled to receive α

and the plurality of address values comprise left-shifted versions of α

.

17. The math unit of claim 11 wherein the address generator comprises a shift register coupled to receive α

and the plurality of address values comprise multiples of α

.

18. A digital signal processor comprising:

a math unit for performing a function on a first LNS operand and a second LNS operand;

an absolute value unit within the math unit for determining a value a by finding the absolute value of the difference of the first and second LNS operands;

a lookup table comprising a plurality of entries, wherein a value of a selected entry is output from the lookup table in response to an address identifying the selected entry;

a first selector for selectively coupling either α

or the plurality of addresses generated from α

to an input of an adder; and

a second selector for selectively coupling the largest of the two LNS operands x and y to an input of the adder, wherein an output of the adder is a LNS result of a function of the first and second LNS operands.