Cyclic flash memory wear leveling
First Claim
1. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a minimum number of memory cells that are simultaneously erasable and wherein incoming blocks of data assigned logical block addresses are programmed into those of the plurality of physical blocks maintained as an erased block pool, comprising:
- identifying at least one of the plurality of physical blocks at a time other than those in the erased block pool for a wear leveling exchange by cycling through addresses of blocks in a characterized order, and exchanging the identified at least one of the plurality of physical blocks with a corresponding number of one or more physical blocks within the erased block pool.
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Accused Products
Abstract
A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated in a manner to level out the wear of the individual blocks through repetitive erasing and re-programming. This may be accomplished without use of counts of the number of times the individual blocks experience erase and re-programming but such counts can optionally aid in carrying out the wear leveling process. Individual active physical blocks are chosen to be exchanged with those of an erased block pool in a predefined order.
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Citations
26 Claims
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1. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a minimum number of memory cells that are simultaneously erasable and wherein incoming blocks of data assigned logical block addresses are programmed into those of the plurality of physical blocks maintained as an erased block pool, comprising:
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identifying at least one of the plurality of physical blocks at a time other than those in the erased block pool for a wear leveling exchange by cycling through addresses of blocks in a characterized order, and exchanging the identified at least one of the plurality of physical blocks with a corresponding number of one or more physical blocks within the erased block pool. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a minimum number of memory cells that are simultaneously erasable and wherein incoming data are programmed into those of the plurality of physical blocks maintained as an erased block pool, comprising:
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identifying at least one of the plurality of physical blocks at a time other than those in the erased block pool for a wear leveling exchange by cycling through addresses of the plurality of physical blocks in a predefined order, monitoring an operational parameter associated with programming data into those of the plurality of physical blocks maintained as an erased block pool, and in response to the monitored operational parameter reaching a preset threshold, exchanging the identified at least one of the plurality of physical blocks with a corresponding number of at least one of the physical blocks within the erased block pool. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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21. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a minimum number of memory cells that are simultaneously erasable and wherein incoming blocks of data have logical block addresses mapped into corresponding physical blocks, comprising:
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identifying at least one of the plurality of physical blocks at a time other than those in the erased block pool for a wear leveling exchange by cycling through the logical block addresses in a predefined order, and exchanging an identified at least one of the plurality of physical blocks with a corresponding number of at least one other of the physical blocks. - View Dependent Claims (22)
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23. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a minimum number of memory cells that are simultaneously erasable, comprising:
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mapping a range of logical block addresses into addresses of a proportion of the plurality of physical blocks that leaves an additional number of physical blocks providing an erased block pool, in response to requests to store data in at least one of the range of logical block addresses, converting said at least one logical block address into an address of at least one physical block residing in the erased block pool and then writing the data into said at least one physical block of the erased block pool, identifying one of the plurality of physical blocks for a wear leveling exchange, after a given number of memory programming operations, exchanging the identified one of the plurality of physical blocks with one of the number of physical blocks residing in the erased block pool, and repeating identifying and exchanging with others of the plurality of physical blocks in a predefined order. - View Dependent Claims (24, 25, 26)
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Specification