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Certified memory-to-memory data transfer between active-active raid controllers

  • US 20060106982A1
  • Filed: 12/22/2005
  • Published: 05/18/2006
  • Est. Priority Date: 09/28/2001
  • Status: Active Grant
First Claim
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1. A system for performing a mirrored posted-write operation, comprising:

  • first and second redundant array of inexpensive disks (RAID) controllers in communication via a PCI-Express link, each comprising a CPU, a write cache memory, and a bus bridge coupled to said CPU, said write cache memory, and said communications link;

    wherein said first bus bridge is configured to transmit a PCI-Express memory write request transaction layer packet (TLP) on said link to said second bus bridge, said TLP comprising payload data and a header, said header including an indication of whether a certification is requested by said first CPU, said certification certifying that said payload data has been written to said second write cache memory;

    wherein if said indication requests said certification, said second bus bridge is configured to automatically transmit said certification to said first bus bridge independent of said second CPU, after writing said payload data to said second write cache memory; and

    wherein said first bus bridge is configured to generate an interrupt to said first CPU in response to receiving said certification.

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