Patching device for a processor
First Claim
1. A patching device for use with a processor having a first non-volatile memory which stores data and a second memory for storing patch data, the patching device comprising:
- a third memory having a plurality of memory locations, each operable to store an address, in the first read-only memory, at which a patch is to be performed;
a comparator which is operable to compare the address of the first memory that is being accessed by the processor with the addresses stored in the third memory;
a control unit which is operable to select between data from the first memory or patch data from the second memory depending on the comparison.
3 Assignments
0 Petitions
Accused Products
Abstract
A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialization process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.
-
Citations
20 Claims
-
1. A patching device for use with a processor having a first non-volatile memory which stores data and a second memory for storing patch data, the patching device comprising:
-
a third memory having a plurality of memory locations, each operable to store an address, in the first read-only memory, at which a patch is to be performed;
a comparator which is operable to compare the address of the first memory that is being accessed by the processor with the addresses stored in the third memory;
a control unit which is operable to select between data from the first memory or patch data from the second memory depending on the comparison. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 11)
-
-
10. A processor arrangement comprising:
-
a processor;
a first non-volatile memory for storing data;
a second memory for storing patch data; and
a patching device comprising;
a third memory having a plurality of memory locations, each operable to store an address, in the first memory, at which a patch is to be performed;
a comparator which is operable to compare the address of the first memory that is being accessed by the processor with the addresses stored in the third memory;
a control unit which is operable to select between data from the first memory or patch data from the second memory depending on the comparison. - View Dependent Claims (12)
-
-
13. A method of patching code in a processor which has a first non-volatile memory which stores data and a second memory for storing patch data, the method comprising:
-
storing, in a plurality of memory locations in a third memory, addresses, in the first memory, at which a patch is to be performed;
comparing the address of the first memory that is being accessed by the processor with the addresses stored in the third memory;
selecting between data from the first memory or patch data from the second memory depending on the comparison. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
-
Specification