Patching device for a processor

• US 20060107104A1
• Filed: 11/04/2005
• Published: 05/18/2006
• Est. Priority Date: 11/04/2004
• Status: Active Grant

• Current Assignee: Proton World International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics NV
• Inventors: Charlier, Vincent, Rahaga, Tiana, Alexandre, Rudolph, Vandersmissen, Yves
• Granted Patent: US 7,844,962 B2
• Time in Patent Office: Days
• US Class Current: 714/8
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/322 for non-sequential address
• CPC Class Codes: G06F 9/328 for runtime instruction patching

Abstract

A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialization process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.

Claims

1. A patching device for use with a processor having a first non-volatile memory which stores data and a second memory for storing patch data, the patching device comprising:

a third memory having a plurality of memory locations, each operable to store an address, in the first read-only memory, at which a patch is to be performed;

a comparator which is operable to compare the address of the first memory that is being accessed by the processor with the addresses stored in the third memory;

a control unit which is operable to select between data from the first memory or patch data from the second memory depending on the comparison.

2. A patching device according to claim 1, wherein the third memory comprises a plurality of patch address registers, each memory location being a register.

3. A patching device according to claim 1, wherein the address of the first memory that is being accessed by the processor is on a bus external to the processor.

4. A patching device according to claim 1, wherein the comparator is operable to perform the comparison of the address of the first memory that is being accessed by the processor with each of the addresses stored in the plurality of memory locations in the third memory, in parallel.

5. A patching device according to claim 1 which further comprises a store of an address, in the second memory, at which the patch data is stored.

6. A patching device according to claim 5, wherein the store is operable to store a base address of an area of the second memory where the patch data is stored and an index which points to a respective patch within that area.

7. A patching device according to claim 1 further comprising at least one memory location for storing an indication of whether a patch instruction code is part of a block of patch code.

8. A patching device according to claim 7, wherein, if the patch instruction code is part of a block of patch code, the control unit is operable to cause a patch address memory location to store the address of the subsequent patch instruction in the second memory.

9. A patching device according to claim 1 further comprising at least one memory location for storing an indication of whether a patch instruction code is a THUMB mode Branch and Link instruction.

11. A patching device according to claim 1 in the form of an integrated circuit.

10. A processor arrangement comprising:

a processor;

a first non-volatile memory for storing data;

a second memory for storing patch data; and

a patching device comprising;

a third memory having a plurality of memory locations, each operable to store an address, in the first memory, at which a patch is to be performed;

a comparator which is operable to compare the address of the first memory that is being accessed by the processor with the addresses stored in the third memory;

a control unit which is operable to select between data from the first memory or patch data from the second memory depending on the comparison.

12. The processor arrangement according to claim 10 in the form of an integrated circuit.

13. A method of patching code in a processor which has a first non-volatile memory which stores data and a second memory for storing patch data, the method comprising:

storing, in a plurality of memory locations in a third memory, addresses, in the first memory, at which a patch is to be performed;

comparing the address of the first memory that is being accessed by the processor with the addresses stored in the third memory;

selecting between data from the first memory or patch data from the second memory depending on the comparison.

14. A method according to claim 13, wherein the comparing of the address of the first memory that is being accessed by the processor is done on a bus external to the processor.

15. A method according to claim 13, wherein the comparing of the address of the first memory that is being accessed by the processor with each of the addresses stored in the plurality of memory locations in the third memory, is done in parallel.

16. A method according to claim 13 further comprising storing of an address, in the second memory, at which the patch data is stored.

17. A method according to claim 16, wherein the storing is of a base address of an area of the second memory where the patch data is stored and of an index which points to a respective patch within that area.

18. A method according to claim 13 further comprising storing an indication of whether a patch instruction code is part of a block of patch code.

19. A method according to claim 18, wherein if the patch instruction code is part of a block of patch code, storing the address of the subsequent patch instruction in the second memory.

20. A method according to claim 13 further comprising storing an indication of whether a patch instruction code is a THUMB mode Branch and Link instruction.