Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys

• US 20060108671A1
• Filed: 11/23/2004
• Published: 05/25/2006
• Est. Priority Date: 11/23/2004
• Status: Active Grant

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Chen, Chang-Sheng, Wang, Peter, Owyang, King, Kasem, Mohammed, Mao, Sen, Kuo, Frank, Ou, Oscar, Jaunay, Serge Robert
• Granted Patent: US 7,394,150 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84345 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/84385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49513 having bonding material between chip and die pad
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/84 using a strap connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.

Claims

1. A semiconductor package comprising:

a semiconductor die having a first terminal on a top surface of said die and at least a second terminal on a bottom surface of said die;

an upper lead frame in electrical contact with said first terminal, said upper lead frame having bent portions extending downward around a pair of opposite edges of said semiconductor die, each of said bent portions terminating in a foot;

a lower lead frame comprising at least two contacts, a first one of said contacts having a plurality of raised mesas formed in a top surface of said first contact, said mesas being separated by valleys;

a first solder layer connecting said first terminal of said die to said upper lead frame;

a second solder layer connecting said second terminal of said die to said first contact of said lower lead frame.

2. The semiconductor package of claim 1 wherein said second solder layer is thicker than said first solder layer.

3. The semiconductor package of claim 1 wherein a groove is formed in a lower surface of said upper lead frame.

4. The semiconductor package of claim 3 wherein said groove is formed in the shape of a cross on said lower surface of said upper lead frame.

5. The semiconductor package of claim 3 wherein said first solder layer extends into said groove.

6. The semiconductor package of claim 1 wherein said second solder layer covers a top surface of each of said mesas.

7. The semiconductor package of claim 1 comprising a third solder layer connecting said upper lead frame to a second one of said contacts of said lower lead frame.

8. The semiconductor package of claim 7 wherein said second one of said contacts has a cavity formed in a top surface thereof.

9. The semiconductor package of claim 1 comprising a protective capsule formed of a molding compound, said molding compounding separating said at least two contacts.

10. The semiconductor package of claim 9 wherein said valleys contain said molding compound.

11. The semiconductor package of claim 1 wherein a passivation layer overlies a portion of said die, said passivation layer being coated with a silicone-based layer.

12. The semiconductor package of claim 1 wherein said upper lead frame comprises a pair of sidewalls that extend downward over a second pair of opposite edges of said die.

13. A package for a vertical MOSFET, said package comprising:

a semiconductor die containing said vertical MOSFET, said die having a drain terminal on a top surface of said die and a source terminal and a gate terminal on a bottom surface of said die;

an upper lead frame in electrical contact with said drain terminal, said upper lead frame having bent portions extending downward around opposite edges of said semiconductor die, each of said bent portions terminating in a foot;

a lower lead frame comprising a source contact, a gate contact, and a pair of drain contacts, each of said source contact and said gate contact having a plurality of raised mesas formed in a top surface thereof, said raised mesas separated by valleys, said source, gate and drain contacts having coplanar bottom surfaces;

a first solder layer connecting said drain terminal to said upper lead frame;

a second solder layer connecting said source terminal to said source contact;

a third solder layer connecting said gate terminal to said gate contact; and

a protective capsule formed of a molding compound, portions of said molding compound separating said first and second contacts.

14. The package of claim 13 wherein said source contact comprises a plurality of paddle-like sections separated by slots, each of said paddle sections comprising a plurality of said raised mesas.