Clock oscillator

• US 20060109058A1
• Filed: 10/19/2005
• Published: 05/25/2006
• Est. Priority Date: 12/31/2002
• Status: Active Grant

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: RadioFrame Networks, Inc. (Motorola Solutions, Inc.)
• Inventors: Keating, Pierce
• Granted Patent: US 7,250,822 B2
• Time in Patent Office: Days
• US Class Current: 331/1.A
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/03 Astable circuits

Abstract

An oscillator circuit and a method of generating an oscillating signal are disclosed. An oscillator comprises a first flip-flop and a second flip-flop coupled with the first flip-flop to provide an oscillating signal. A method of generating an oscillating signal comprises providing the oscillating signal as a first clock input to a first flip flop, inverting the oscillating signal and providing the inverted oscillating signal as a second clock input to a second flip flop, using the output of the first flip flop and the output of the second flip flop to generate a combined output that alternates between a logic low level and a logic high level, and using the combined output to sustain the oscillation of the oscillating signal.

Claims

1. An oscillator comprising:

a first flip-flop configured to receive as a first clock input an output oscillating signal associated with the oscillator;

a second flip-flop configured to receive as a second clock input an inverted output oscillating signal; and

a combining element configured to receive and combine a first output of the first flip-flop and a second output of the second flip-flop to provide the output oscillating signal.

2. An oscillator as recited in claim 1, wherein the oscillating signal has an oscillation frequency close to a maximum toggling frequency of the flip-flop.

3. An oscillator as recited in claim 1, wherein the first and the second flip-flops are configured in a feedback arrangement.

4. An oscillator as recited in claim 1, wherein the first and the second flip-flops are configured in a feedback arrangement wherein the oscillating signal is fed back to a first clock input of the first flip-flop and a second clock input of the second flip-flop.

5. An oscillator as recited in claim 1, wherein the first and the second flip-flops are configured in a cross-coupled feedback arrangement.

6. An oscillator as recited in claim 1, wherein:

the first and the second flip-flops are configured in a cross-coupled feedback arrangement wherein the oscillating signal is fed back to a first clock input of the first flip-flop and a second clock input of the second flip-flop, and

the oscillating signal has a positive transition and a negative transition and clock inputs of the first and the second flip-flops are configured to trigger on opposite transitions of the oscillating signal.

7. An oscillator as recited in claim 1, wherein the first and the second flip-flops are configured in a cross-coupled feedback arrangement to toggle alternately.

8. An oscillator as recited in claim 1, wherein the oscillating signal is applied to a circuit that includes a circuit flip-flop, and the first and second flip-flops are substantially the same type as the circuit flip-flop.

9. An oscillator as recited in claim 1, wherein the oscillating signal is applied to a circuit, and the oscillator resides on the same die as the circuit.

10. An oscillator as recited in claim 1, further comprising an interface for receiving a startup signal configure to start oscillation.

11. An oscillator as recited in claim 1, further comprising a clock buffer configured to buffer the oscillating signal.

12. An oscillator as recited in claim 1, wherein the oscillating signal is provided to a primary circuit via a primary circuit buffer and further comprising an oscillating signal buffer configured to buffer the oscillating signal in the same manner that the primary circuit buffer buffers the oscillating signal as provided to the primary circuit.

13. An oscillator as recited in claim 1, wherein the oscillating signal is sent to a field programmable gate array (FPGA).

14. An oscillator as recited in claim 1, wherein the oscillating signal is sent to an application specific integrated circuit (ASIC).

15. An oscillator as recited in claim 1, wherein the oscillating signal is monitored.

16. An oscillator as recited in claim 1, wherein the oscillating signal is monitored and the oscillator is restarted if it is determined that the output has ceased to oscillate.

22. An oscillator as recited in claim 1, further comprising an inverter configured to invert the output oscillating signal and provide the inverted output oscillating signal.

23. An oscillator as recited in claim 22, wherein the inverter and the second flip-flop are integrated into a single circuit element.

24. An oscillator as recited in claim 1, wherein the combining element comprises an XOR gate.

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