NAND flash memory device capable of improving read speed

• US 20060109715A1
• Filed: 11/22/2005
• Published: 05/25/2006
• Est. Priority Date: 11/22/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Seung-Jae, Park, Jung-Hoon
• Granted Patent: US 7,227,782 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A NAND flash memory device according to the present invention is provided which includes a first page buffer circuit reading main data bits from the main field during a read operation, a second page buffer circuit reading redundant data bits from the redundancy field during the read operation, a first column gate circuit configured to select a part of the read main data bits and a part of the read redundant data bits in response to first column selection signals at the same time, and a second column gate circuit configured to select a part of the selected main data bits in response to second column selection signals.

Claims

1. A NAND flash memory device including a main field and a redundant field comprising:

a first page buffer circuit reading main data bits from the main field during a read operation;

a second page buffer circuit reading redundant data bits from the redundancy field during the read operation;

a first column gate circuit configured to select a part of the main data bits read from the main field and at the same time a part of the redundant data bits read from the redundant field in response to first column selection signals; and

a second column gate circuit configured to select a part of the selected main data bits in response to second column selection signals.

2. The device of claim 1, further comprising:

a multiplexer circuit receiving the main data bits from the second column gate circuit and the redundant data bits from the first column gate circuit; and

a redundancy control circuit configured to control the multiplexer circuit in response to a column address.

3. The device of claim 2, wherein if the column address is a defective column address, the redundancy control circuit controls the multiplexer circuit so that one of the main data bits input to the multiplexer circuit is replaced with one of the selected redundant data bits.

4. The device of claim 2, wherein if the column address is not a defective column address, the redundancy control circuit controls the multiplexer circuit so that main data bits input to the multiplexer circuit are all output regardless of the selected redundant data bits.

5. The device of claim 2, wherein the redundancy control circuit is operated in response to a column address and generates the first selection signals for selecting main data bits selected by the second column gate circuit, respectively and the second selection signals for selecting one of the selected redundant data bits.

6. The device of claim 5, wherein the multiplexer circuit includes multiplexers corresponding to the first selection signals, respectively.

7. The device of claim 6, wherein each of the multiplexers selects corresponding main data bit or one of the selected redundancy data bits in response to a corresponding first selection signal and the second selection signals.

8. A NAND flash memory device including a main field and a redundant field comprising:

a first page buffer circuit reading main data bits form the main field during a read operation;

a second page buffer circuit reading redundant data bits from the redundant field during the read operation;

a column decoder circuit generating first column selection signals and second column selection signals in response to a column address;

a first column gate circuit configured to simultaneously select a part of the main data bits read from the main field and a part of the redundant data bits read from the redundant field in response to the first column selection signals;

a second column gate circuit configured to select a part of the selected main data bits in response to the second column selection signals;

a multiplexer circuit receiving main data bits from the second column gate circuit, and redundant data bits from the first column gate circuit; and

a redundancy control circuit configured to control the multiplexer circuit in response to the column address.

9. The device of claim 8, wherein if the column address is a defective column address, the redundancy control circuit controls the multiplexer circuit so that one of main data bits input to the multiplexer circuit is replaced with one of the selected redundant data bits.

10. The device of claim 9, wherein if the column address is not a defective column address, the redundancy control circuit controls the multiplexer circuit so that all main data bits input to the multiplexer circuit are output regardless of the selected redundant data bits.

11. The device of claim 9, wherein the redundancy control circuit is operated in response to a column address and generates first selection signals for selecting respective main data bits selected by the second column gate circuit and second selection signals for selecting one of the selected redundant data bits.

12. The device of claim 11, wherein the multiplexer circuit includes multiplexers corresponding to the first selection signals, respectively.

13. The device of claim 12, wherein each of the multiplexers selects a corresponding main data bit or one of the selected redundant data bits in response to a corresponding first selection signal and the second selection signals.

14. A reading method of a NAND flash memory device having a main field and a redundancy field comprising:

simultaneously reading main data bits from the main field and redundant data bits from the redundant field during a read operation;

generating first column selection signals and second column selection signals in response to a column address;

simultaneously selecting a part of the main data bits read from the main field and a part of the redundant data bits read from the redundant field in response to the first column selection signals;

selecting a part of the selected main data bits in response to the second column selection signals; and

selectively outputting main data bits and redundant data bits in accordance with redundancy information.

15. The method of claim 14, wherein the redundancy information is produced by the column address.