Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys
First Claim
1. A method of fabricating a semiconductor package comprising:
- providing a lower lead frame, said lower lead frame having at least a first contact and a second contact;
partially etching said lower lead frame so as to form a plurality of raised mesas in said first contact, said mesas being separated by valleys;
dispensing a first plurality of solder paste drops on said mesas;
placing a semiconductor die on said first plurality of solder paste drops;
performing a first reflow of said first plurality of solder paste drops so as form a first solder layer between said die and said lower lead frame;
dispensing a second plurality of solder paste drops on a top surface of said die;
placing an upper lead frame on said second plurality of solder paste drops, said upper lead frame comprising bent portions at opposite ends of said upper lead frame, each of said bent portions extending downward and terminating in a foot;
performing a second reflow of said plurality of solder paste drops and said first solder layer.
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Accused Products
Abstract
A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.
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Citations
4 Claims
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1. A method of fabricating a semiconductor package comprising:
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providing a lower lead frame, said lower lead frame having at least a first contact and a second contact;
partially etching said lower lead frame so as to form a plurality of raised mesas in said first contact, said mesas being separated by valleys;
dispensing a first plurality of solder paste drops on said mesas;
placing a semiconductor die on said first plurality of solder paste drops;
performing a first reflow of said first plurality of solder paste drops so as form a first solder layer between said die and said lower lead frame;
dispensing a second plurality of solder paste drops on a top surface of said die;
placing an upper lead frame on said second plurality of solder paste drops, said upper lead frame comprising bent portions at opposite ends of said upper lead frame, each of said bent portions extending downward and terminating in a foot;
performing a second reflow of said plurality of solder paste drops and said first solder layer. - View Dependent Claims (2, 3, 4)
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Specification