Method of increasing deposition rate of silicon dioxide on a catalyst

• US 20060110936A1
• Filed: 12/29/2005
• Published: 05/25/2006
• Est. Priority Date: 08/31/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Derderian, Garo J., Hill, Chris W.
• Granted Patent: US 8,110,891 B2
• Time in Patent Office: Days
• US Class Current: 438/778
• CPC Class Codes: C23C 16/403 of aluminium, magnesium or beryllium
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: C23C 16/45534 Use of auxiliary reactants other than used for contributing to the composition of the main film, e.g. catalysts, activators or scavengers
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/316 composed of oxides or glassy oxides or oxide based glass
• CPC Class Codes: H01L 21/31683 of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
• CPC Class Codes: H01L 21/31695 Deposition of porous oxides or porous glassy oxides or oxide based porous glass

Abstract

Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to an organoaluminum catalyst to form a monolayer over the surface, remote plasmas of oxygen and nitrogen to convert the organoaluminum layer to a porous aluminum oxide layer, and a silanol precursor to form a thick layer of silicon dioxide over the porous oxide layer. The process provides an increased rate of deposition of the silicon dioxide, with each cycle producing a thick layer of silicon dioxide of about 120 Å over the layer of porous aluminum oxide.

Claims

1. A semiconductor device, comprising:

a laminate of alternating layers of a porous aluminum oxide monolayer and an about 100-300 Å

thick layer of silicon dioxide.

2. A semiconductor device, comprising a layer of silicon dioxide overlying a monolayer of a porous aluminum oxide.

3. A semiconductor device, comprising an about 100-300 Å

thick layer of silicon dioxide overlying a monolayer of a porous aluminum oxide.

4. A semiconductor device, comprising a plurality of about 100-300 Å

thick layers of silicon dioxide, each of said layers overlying a monolayer of a porous aluminum oxide.

5. In a semiconductor device, a composite insulating material comprising a plurality of about 100-300 Å

thick layers of silicon dioxide, each of said layers overlying a monolayer of a porous aluminum oxide.

6. In a semiconductor device, a composite insulating material comprising a plurality of alternating layers of a monolayer of porous aluminum oxide and an about 100-300 Å

thick silicon dioxide layer.

7. In a semiconductor device, an isolation structure comprising alternating layers of a monolayer of porous aluminum oxide and an about 100-300 Å

thick silicon dioxide layer.

8. The device of claim 7, wherein the isolation structure is selected from the group consisting of a shallow trench isolation, a gate spacer, a spacer between wordlines, and a buried digit line spacer.

9. The device of claim 7, selected from the group consisting of a programmable memory device, programmable resistor and capacitor device, optical device, and sensor.

10. In a semiconductor device, an interlayer dielectric comprising a composite of alternating layers of a monolayer of porous aluminum oxide and an about 100-300 Å

thick silicon dioxide layer.

11. In a semiconductor device, a shallow trench isolation region comprising alternating monolayers of porous aluminum oxide and about 100-300 Å

thick layers of silicon dioxide.

12. In a semiconductor device, an insulating fill situated within an opening and comprising a alternating layers of a monolayer of porous aluminum oxide and an about 100-300 Å

thick layer of silicon dioxide.

13. The device of claim 12, wherein the insulating fill is situated in a trench opening in a substrate.

14. The device of claim 12, wherein the insulating fill is situated in a high aspect ratio opening in a substrate between active components.

15. The device of claim 14, wherein the aspect ratio is about 20-30:

1.

16. An isolation structure in a semiconductor device, the isolation structure comprising a laminate of a plurality of alternating layers of a porous aluminum oxide monolayer and an about 100-300 Å

thick silicon dioxide layer.

17. The isolation structure of claim 16, selected from the group consisting of a interlayer dielectric layer, a shallow trench isolation device, and an insulating plug.

18. A semiconductor die, comprising an isolation structure comprising a laminate of a plurality of alternating layers of a porous aluminum oxide monolayer and an about 100-300 Å

thick layer of silicon dioxide.

19. A wafer, comprising an isolation structure comprising a laminate of a plurality of alternating layers of a porous aluminum oxide monolayer and an about 100-300 Å

thick layer of silicon dioxide.

20. An integrated circuit supported by a substrate and comprising a composite insulating element comprising a plurality of about 100-300 Å

thick layers of silicon dioxide, each of said layers overlying a monolayer of a porous aluminum oxide.

21. An integrated circuit supported by a substrate and comprising an isolation structure comprising a plurality of alternating layers of a porous aluminum oxide monolayer and an about 100-300 Å

thick layer of silicon dioxide

22. An integrated circuit, comprising:

an array of memory cells;

internal circuitry connected to the memory cell array; and

an isolation structure comprising alternating layers of a porous aluminum oxide monolayer and an about 100-300 Å

thick layer of silicon dioxide.

23. A system comprising:

a microprocessor; and

a memory device coupled to the microprocessor, the memory device comprising an isolation structure comprising a plurality of alternating layers of a porous aluminum oxide monolayer and an about 100-300 Å

thick layer of silicon dioxide.

24. An electronic system, comprising:

a processor; and

an integrated circuit in communication with the processor, the integrated circuit comprising an isolation structure comprising a plurality of alternating layers of a porous aluminum oxide monolayer and an about 100-300 Å

thick layer of silicon dioxide.

25. The system of claim 24, wherein the isolation structure comprises a trench isolation region.

26. The system of claim 24, wherein the isolation structure comprises an interlayer dielectric layer.

27. The system of claim 24, wherein the integrated circuit comprises a memory circuit.

28. The system of claim 27, wherein the memory circuit is a DRAM memory circuit.

29. A circuit module, comprising a plurality of dies, at least one die comprising an isolation structure comprising a composite of a plurality of alternating layers of a porous aluminum oxide monolayer and an about 100-300 Å

thick layer of silicon dioxide.

30. The circuit module of claim 29, selected from the group consisting of a memory module, device driver, power module, communication modem, processor module, and application-specific module.

31. The circuit module of claim 30, comprising a multilayer, multichip module.

32. The circuit module of claim 30, being a subcomponent of an electronic system.

33. The circuit module of claim 32, wherein the electronic system is selected from the group consisting of a clock, television, cell phone, personal computer, automobile, industrial control system, and an aircraft.

34. The circuit module of claim 32, wherein the electronic system comprises a user interface selected from the group consisting of a keyboard, monitor, display, printer, and speaker.

35. The circuit module of claim 32, wherein the electronic system comprises a processor.

36. The circuit module of claim 35, further comprising a memory system.

37. The circuit module of claim 36, further comprising a component selected from the group consisting of a modem, and a device interface card.

38. The circuit module of claim 29, wherein the isolation structure is part of a circuit selected from the group consisting of Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Flash memory, Synchronous Graphics Random Access Memory (SGRAM), Synchronous Dynamic Random Access Memory (SDRAM), SDRAM II, Double Data Rate SDRAM (DDR SDRAM), and Synchlink.