Systolic de-multiplexed finite impulse response filter array architecture for linear and non-linear implementations

• US 20060112157A1
• Filed: 11/19/2004
• Published: 05/25/2006
• Est. Priority Date: 11/19/2004
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Song, William S.
• Granted Patent: US 7,480,689 B2
• Time in Patent Office: Days
• US Class Current: 708/300
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H03H 2220/06 Systolic

Abstract

Described is a finite impulse filter response (FIR) filter for use by signal processors. A demultiplexer receives input data samples at an input data rate. The FIR filter includes a plurality of computational units arranged in a systolic array of taps and phases. Each computational unit operates at an array clock rate that is slower than the input data rate. During each array clock cycle, the phases produce a plurality of output data samples that provides an output data rate equal to the input data rate. The FIR filters can thus support an output data rate equal to the input data rate although the input data rate exceeds the maximum clock speed of the processor. The FIR filter can also operate at a reduced array clock speed, while continuing to produce an output data rate equal to the input data rate, to increase the power efficiency of the processor.

Claims

1. A signal processor, comprising:

a demultiplexer receiving input data samples at an input data rate; and

a finite impulse response (FIR) filter in communication with the demultiplexer for obtaining input data samples therefrom, the FIR filter including a plurality of computational units arranged in an array having a plurality of taps and a plurality of phases, each computational unit operating synchronously at an array clock rate that is slower than the input data rate.

2. The signal processor of claim 1, wherein the array has N phases, where N is any integer greater than 1, and wherein the array clock rate at which each computational unit operates is approximately equal to 1/N of the input data rate.

3. The signal processor of claim 1, wherein the plurality of phases produces during each array clock cycle a plurality of output data samples that provides an output data rate equal to the input data rate.

4. The signal processor of claim 1, wherein the plurality of phases produces during each array clock cycle a plurality of output data samples that provides an output data rate that is greater than the input data rate.

5. The signal processor of claim 1, wherein the plurality of phases produces during each array clock cycle an output data rate that is less than the input data rate.

6. The signal processor of claim 1, further comprising a set of coefficients with each coefficient in the set being associated with one of the taps of the FIR filter, each computational unit of a given tap using the coefficient associated with that tap to multiply an input data sample received by that computational unit.

7. The signal processor of claim 1, wherein during each array clock cycle the demultiplexer forwards input data samples concurrently to each phase and to each tap of computational units.

8. The signal processor of claim 1, wherein the demultiplexer forwards input data samples to the phases of computational units according to a round robin sequence.

9. A finite impulse response (FIR) filter for filtering input data samples, the FIR filter comprising a plurality of computational units arranged in a systolic array having a plurality of columns and a plurality of rows, each column of computational units corresponding to one of a tap and a phase and each row of computational units corresponding to the other of a tap and a phase, each computational unit in one phase other than a last phase being in communication with a first computational unit in a neighboring tap over a first signal line for communicating a computed value and with a second computational unit in the neighboring tap over a second signal line for communicating an input data sample.

10. The FIR filter of claim 9, wherein the array has N phases, where N is any integer greater than 1, each computational unit operates at an array clock rate that is equal to 1/N of an input data rate of the input data samples, and the plurality of phases of computational units produces during each array clock cycle an output data rate equal to the input data rate.

11. The FIR filter of claim 9, wherein the array has N phases, where N is any integer greater than 1, each computational unit operates at an array clock rate that is equal to 1/N of an input data rate of the input data samples, and the plurality of phases of computational units produces during each array clock cycle an output data rate that is less than the input data rate.

12. The FIR filter of claim 9, wherein the array has N phases, where N is any integer greater than 1, each computational unit operates at an array clock rate that is slower than an input data rate of the input data samples, and the plurality of phases of computational units produces during each array clock cycle an output data rate that is greater than the input data rate.

13. The FIR filter of claim 9, wherein, for each computational unit in one phase other than the last phase, the first computational unit in the neighboring tap is in the same phase as that computational unit and the second computational unit in the neighboring tap is in a different phase from that computational unit.

14. The FIR filter of claim 9, further comprising a set of coefficients, each coefficient in the set being associated with one of the taps of the FIR filter, each computational unit of a given tap using the coefficient associated with that tap to multiply an input data sample received by that computational unit.

15. A finite impulse response (FIR) filter for filtering input data samples, comprising:

a plurality of computational units arranged in a systolic array having a plurality of columns and a plurality of rows, each column of computational units corresponding to one of a tap and a phase and each row of computational units corresponding to the other of a tap and a phase, each computational unit in a tap other than a last tap comprising;

a first input signal line for receiving an input data sample,

a second input signal line for receiving a coefficient,

a third input signal line for receiving a supplied value,

circuitry for computing a value based on the received input data sample, the coefficient, and the supplied value,

a first output signal line for communicating the value computed by that computational unit to a computational unit in a neighboring tap, and

a second output signal line for communicating the received input data sample to a computational unit in a neighboring phase of the neighboring tap.

16. The FIR filter of claim 15, wherein the array has N phases, where N is any integer greater than 1, each computational unit operates at an array clock rate that is equal to 1/N of an input data rate of the input data samples, and the plurality of rows of computational units produces during each array clock cycle an output data rate equal to the input data rate.

17. The FIR filter of claim 15, wherein the array has N phases, where N is any integer greater than 1, each computational unit operates at an array clock rate that is equal to 1/N of an input data rate of the input data samples, and the plurality of phases of computational units produces during each array clock cycle an output data rate that is less than the input data rate.

18. The FIR filter of claim 15, wherein the array has N phases, where N is any integer greater than 1, each computational unit operates at an array clock rate that is slower than an input data rate of the input data samples, and the plurality of phases of computational units produces during each array clock cycle an output data rate that is greater than the input data rate.

19. The FIR filter of claim 15, further comprising a delay disposed between the first input signal line and the second output signal line for holding an input data sample for an array clock cycle before that input data sample passes to the computational unit in the neighboring phase and neighboring tap.

20. The FIR filter of claim 15, further comprising a set of coefficients with each coefficient in the set being associated with one of the taps of the FIR filter, each computational unit of a given tap using the coefficient associated with that tap to multiply an input data sample received by that computational unit.

21. A signal processor, comprising:

a demultiplexer receiving input data samples; and

a first finite impulse response (FIR) filter in communication with the demultiplexer for obtaining the input data samples therefrom, the first FIR filter including a first plurality of computational units arranged in an array having a plurality of taps and a plurality of phases and a first set of coefficients used by the first plurality of computational units to compute values based on the input data samples; and

a second FIR filter in communication with the demultiplexer for obtaining the input data samples therefrom, the second FIR filter including a second plurality of computational units arranged in an array having a plurality of taps and a plurality of phases and a second set of coefficients different from the first set of coefficients, the second set of coefficients being used by the second plurality of computational units to compute values based on the input data samples.

22. The signal processor of claim 21, wherein the first FIR filter receives the input data samples from the demultiplexer one array clock cycle after the second FIR filter receives the input data samples.

23. The signal processor of claim 21, wherein at least one of the computational units in a last phase of the second FIR filter is in communication with one of the computational units in a first phase of the first FIR filter for communicating an input data sample during each array clock cycle.

24. The signal processor of claim 21, wherein the demultiplexer receives the input data samples at an input data rate and wherein each computational unit in the first and second FIR filters operates at an array clock rate that is slower than the input data rate, the plurality of phases of computational units of each FIR filter producing during each array clock cycle an output data rate equal to the input data rate.

25. The signal processor of claim 21, wherein the demultiplexer receives the input data samples at an input data rate and wherein each computational unit in the first and second FIR filters operates at an array clock rate that is slower than the input data rate, the plurality of phases of computational units of each FIR filter producing during each array clock cycle an output data rate that is less than the input data rate.

26. The signal processor of claim 21, wherein the demultiplexer receives the input data samples at an input data rate and wherein each computational unit in the first and second FIR filters operates at an array clock rate that is slower than the input data rate, the plurality of phases of computational units of each FIR filter producing during each array clock cycle an output data rate that is greater than the input data rate.

27. The signal processor of claim 21, wherein during each array clock cycle the demultiplexer forwards input data samples concurrently to each tap and to each phase of computational units.

28. The signal processor of claim 27, wherein the demultiplexer forwards input data samples to the phases of computational units according to a round robin sequence.

29. A method of linearly filtering input data samples, comprising:

receiving input data samples at an input data rate;

forwarding the input data samples to an array of computational units of a finite impulse filter (FIR) having a plurality of taps and a plurality of phases; and

operating each computational unit at an array clock rate that is slower than the input data rate.

30. The method of claim 29, further comprising producing by the plurality of phases an output data rate that is equal to the input data rate during each array clock cycle.

31. The method of claim 29, further comprising producing by the plurality of phases an output data rate that is greater than the input data rate during each array clock cycle.

32. The method of claim 29, further comprising producing by the plurality of phases an output data rate that is less than the input data rate during each array clock cycle.

33. The method of claim 29, wherein the step of producing comprises:

receiving by each tap of computational units a plurality of input data samples;

computing by each computational unit a value based on an input data sample received by that computational unit;

communicating by each tap of computational units other than a last tap the values computed by those computational units to the computational units in a neighboring tap;

communicating by each tap of computational units other than a last tap input data samples received by those computational units during a previous array clock cycle to the computational units in a neighboring phase in the neighboring tap;

communicating by the last tap of computational units a plurality of computed values corresponding to the output data samples.

34. The method of claim 29, further comprising multiplying input data samples received by the computational units in a given tap by the same coefficient.

35. The method of claim 29, wherein the step of forwarding includes forwarding the received input data samples concurrently to a first tap and a first phase of the array.

36. The method of claim 29, wherein the step of forwarding includes forwarding the input data samples to the computational units in the first tap of the array in accordance with a round robin sequence.