Dynamic control of memory access speed
First Claim
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1. A memory system, comprising:
- memory; and
a memory controller configured to generate a plurality of control signals to access the memory, the memory controller further being configured to adjust the timing between the control signals to change the memory access speed as a function of a parameter related to the operation of the memory system.
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Abstract
A memory system is disclosed in which the access speed may be adjusted. The memory system may include memory and a memory controller. The memory controller may be configured to generate a plurality of control signals to access the memory, and adjust the timing between the control signals to change the memory access speed as a function of a parameter related to the operation of the memory system.
38 Citations
23 Claims
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1. A memory system, comprising:
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memory; and
a memory controller configured to generate a plurality of control signals to access the memory, the memory controller further being configured to adjust the timing between the control signals to change the memory access speed as a function of a parameter related to the operation of the memory system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of accessing memory in a memory system, comprising:
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generating a plurality of control signals to access the memory; and
adjusting the timing between the control signals to change the memory access speed as a function of a parameter related to the operation of the memory system. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A memory system, comprising:
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memory; and
a memory controller comprising means for generating a plurality of control signals to access the memory, and means for adjusting the timing between the control signals to change the memory access speed as a function of a parameter related to the operation of the memory system.
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Specification