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Dynamic control of memory access speed

  • US 20060112250A1
  • Filed: 11/24/2004
  • Published: 05/25/2006
  • Est. Priority Date: 11/24/2004
  • Status: Active Grant
First Claim
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1. A memory system, comprising:

  • memory; and

    a memory controller configured to generate a plurality of control signals to access the memory, the memory controller further being configured to adjust the timing between the control signals to change the memory access speed as a function of a parameter related to the operation of the memory system.

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