Test structure of semiconductor device

• US 20060113534A1
• Filed: 10/05/2005
• Published: 06/01/2006
• Est. Priority Date: 11/30/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc., Infineon Technologies AG, Samsung Electronics Co. Ltd.
• Original Assignee: Infineon Technologies AG, International Business Machines Corporation, Samsung Electronics Co. Ltd.
• Inventors: Luo, Zhijiong, Greene, Brian J., Knoefler, Roman, Eller, Manfred, Ku, Ja-hum, Sun, Min-chul
• Granted Patent: US 7,501,651 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.

Claims

1. A test structure of a semiconductor device comprising:

first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively;

a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions; and

first and second pads electrically connected respectively to the first and second junction regions for receiving an application of an electrical signal and outputting a detected signal, wherein the first and second pads are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.

2. The test structure of claim 1, wherein the first and second pads formed on the same level as the lower part of the metal layer is an interconnect layer formed on a field isolation region of the semiconductor substrate.

3. The test structure of claim 2, further comprising a first connecting portion which is formed on the first active region and connects the first pad to the first junction region;

and a second connecting portion which is formed on the second active region and connects the second pad to the second junction region.

4. The test structure of claim 3, wherein the first and second connecting portions include wells having the same conductivity type as the first and second junction regions, insulating layers formed on the wells, and auxiliary pads electrically connected to the first and second pads.

5. The test structure of claim 1, wherein the first and second pads formed on the same level as the semiconductor substrate are well pads which are formed on a portion of the lower parts of the first and second junction regions and have the same conductivity type as the first and second junction regions.

6. The test structure of claim 1, wherein first and second pad active regions respectively included in the first and second active regions having the well pads formed thereon are connected to regions other than the first and second pad active regions of the first and second active regions through contact active regions that have a width having the margin resolution of a photolithography process.

7. The test structure of claim 1, wherein the first and second active regions are arranged in a cross-finger array.

8. The test structure of claim 1, wherein the first pad is connected to a ground voltage or a negative voltage and the second pad is connected to the negative voltage.

9. A test structure of a semiconductor device comprising:

first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively;

a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions;

first and second pads which are formed on the semiconductor substrate and the same level as a lower part of a metal layer; and

first and second connecting portions which connect the first and second pads to the first and second junction regions, respectively.

10. The test structure of claim 9, wherein the first and second pads are formed on a field isolation region defining the first and second active regions.

11. The test structure of claim 9, wherein the first and second connecting portions include wells having the same conductivity type as the first and second junction regions, insulating layers formed on the wells, and auxiliary pads electrically connected to the first and second pads, respectively.

12. The test structure of claim 9, wherein the first and second active regions include first and second main active regions arranged in a cross-finger array and a plurality of first and second sub-active regions which are branched off from the first and second main active regions, respectively, and wherein the first and second connecting portions are arranged on the first and second main active regions in a cross-finger array.

13. The test structure of claim 12, wherein the first and second sub-active regions are connected to the first and second main active regions through contact portions that have a width having the margin resolution of a photolithography process.

14. The test structure of claim 12, wherein the first and second sub-active regions include first and second common sub-active regions and a plurality of first and second branch sub-active regions which are branched off from the first and second common sub-active regions, respectively.

15. The test structure of claim 14, wherein the first and second branch sub-active regions have widths having the margin resolution of a photolithography process.

16. The test structure of claim 14, wherein the first and second branch sub-active regions are formed in a cross-finger array.

17. The test structure of claim 9, wherein the first pad is connected to a ground voltage or a negative voltage and the second pad is connected to a negative voltage.

18. A test structure of a semiconductor device comprising:

first and second active regions which are electrically isolated from each other and in which silicided first and second junction regions are formed, respectively;

a semiconductor substrate or a well which electrically connects lower parts of the first and second junction regions to each other and has a conductivity type different from the first and second junction regions; and

first and second well pads which are formed on a portion of the lower parts of the first and second junction regions and have the same conductivity type as the first and second junction regions.

19. The test structure of claim 18, wherein first and second pad active regions respectively included in the first and second active regions having the well pads formed thereon are connected to regions other than the first and second pad active regions of the first and second active regions through contact active regions that have a width having the margin resolution of a photolithography process.

20. The test structure of claim 18, wherein the first and second active regions include first and second main active regions arranged in a cross-finger array and a plurality of first and second sub-active regions which are connected to the first and second main active regions to face and opposite to the same, the first and second sub-active regions being arranged between each of the first and second main active regions.

21. The test structure of claim 20, wherein the first and second sub-active regions include first and second common sub-active regions and a plurality of first and second branch sub-active regions which are branched off from the first and second common sub-active regions, respectively.

22. The test structure of claim 21, wherein the first and second branch sub-active regions have widths having the margin resolution of a photolithography process.

23. The test structure of claim 21, wherein the first and second branch sub-active regions are formed in a cross-finger array.

24. The test structure of claim 18, wherein the first well pad is connected to a ground voltage or a negative voltage and the second well pad is connected to the negative voltage.