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Twin EEPROM memory transistors with subsurface stepped floating gates

  • US 20060113583A1
  • Filed: 01/17/2006
  • Published: 06/01/2006
  • Est. Priority Date: 04/25/2003
  • Status: Abandoned Application
First Claim
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1. In an EEPROM transistor in a memory array of the EEPROM type fabricated in a silicon wafer with an oxide coating on the wafer surface, with a source, drain and floating gate, the improvement comprising a step in floating gate extending at least partially below the wafer surface and a first capacitor control element with first and second capacitor plates, the first plate connected to the floating gate.

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