Twin EEPROM memory transistors with subsurface stepped floating gates

• US 20060113583A1
• Filed: 01/17/2006
• Published: 06/01/2006
• Est. Priority Date: 04/25/2003
• Status: Abandoned Application

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lojek, Bohumil
• Application Number:
  US11/332,908
• Publication Number:
  US 20060113583A1
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/7886 Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/23 with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory array with memory cells arranged in rows and columns with each cell having twin EEPROMs featuring subsurface stepped floating gates for electric field concentration. The twin EEPROMs employ only a single layer of poly, one portion being a floating gate of each EEPROM and another portion being word lines. The twin EEPROMs share a common subsurface electrode by having diffused control lines and a diffused bit line. The two EEPROMs are symmetric across the common electrode.

Claims

1. In an EEPROM transistor in a memory array of the EEPROM type fabricated in a silicon wafer with an oxide coating on the wafer surface, with a source, drain and floating gate, the improvement comprising a step in floating gate extending at least partially below the wafer surface and a first capacitor control element with first and second capacitor plates, the first plate connected to the floating gate.

2. The transistor of claim 1 having a second capacitor connected to a source or drain electrode.

3. The transistor of claim 1 wherein said second capacitor has plates associated with a word line and a bit line of the memory array.

4. The transistor of claim 1 wherein said step has top and bottom corners.