Integrated circuit including silicon wafer with annealed glass paste

• US 20060113639A1
• Filed: 01/10/2006
• Published: 06/01/2006
• Est. Priority Date: 10/15/2002
• Status: Abandoned Application

• Current Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat
• Application Number:
  US11/328,979
• Publication Number:
  US 20060113639A1
• Time in Patent Office: Days
• US Class Current: 257/634
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/166 : Material
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H03L 1/026 : by using a memory for digitally storing correction values H03L1/025 takes precedence
• CPC Class Codes: H03L 7/197 : a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/1976 : using a phase accumulator for controlling the counter or frequency divider

Abstract

An integrated circuit (IC) package comprises an IC wafer and an annealed glass paste (AGP) layer that is arranged adjacent to the IC wafer. A molding material encapsulates at least part of the IC wafer and the AGP layer. The AGP layer is arranged on at least one side of the IC wafer. The AGP layer is arranged on a plurality of disjoint areas on at least one side of the IC wafer. A layer of a conductive material is arranged on a portion of the AGP layer.

Claims

1. An integrated circuit (IC) package, comprising:

an IC wafer; and

an annealed glass paste (AGP) layer that is arranged adjacent to said IC wafer.

2. The IC package of claim 1 further comprising a molding material that encapsulates at least part of said IC wafer and said AGP layer.

3. The IC package of claim 1 wherein said AGP layer is arranged on at least one side of said IC wafer.

4. The IC package of claim 1 wherein said AGP layer is arranged on a plurality of disjoint areas on at least one side of said IC wafer.

5. The IC package of claim 1 further comprising a layer of a conductive material that is arranged on a portion of said AGP layer.

6. The IC package of claim 2 wherein said IC wafer comprises a circuit component arranged in said IC wafer, wherein said AGP layer is arranged between said circuit component and said molding material.

7. The IC package of claim 6 wherein said circuit component comprises at least one of an oscillator and an inductor.

8. The IC package of claim 7 wherein said inductor comprises a spiral inductor.

9. The IC package of claim 2 wherein said molding material encapsulates a portion of said IC wafer.

10. The IC package of claim 1 wherein said AGP layer comprises a glass frit.

11. The IC package of claim 1 wherein said AGP layer is arranged adjacent to said IC wafer using one of a screen printing, dipping and masking.

12. The IC package of claim 5 wherein said conductive material comprises one of a conductive epoxy and a conductive epoxy paint.

13. The IC package of claim 5 wherein said layer of said conductive material is arranged on said AGP layer by dipping said IC package in a container containing said conductive material.

21. The method of claim 7 wherein said inductor comprises a spiral inductor.

24. The method of claim 1 further comprising arranging said AGP layer adjacent to said IC wafer using one of a screen printing, dipping and masking.

14. A method for providing an integrated circuit (IC) package, comprising:

providing an IC wafer; and

arranging an annealed glass paste (AGP) layer adjacent to said IC wafer.

15. The method of claim 14 further comprising encapsulating at least part of said IC wafer and said AGP layer using a molding material.

16. The method of claim 14 further comprising arranging said AGP layer on at least one side of said IC wafer.

17. The method of claim 14 further comprising arranging said AGP layer on a plurality of disjoint areas on at least one side of said IC wafer.

18. The method of claim 14 further comprising arranging a layer of a conductive material on a portion of said AGP layer.

19. The method of claim 15 wherein said IC wafer comprises a circuit component arranged in said IC wafer and further comprising arranging said AGP layer between said circuit component and said molding material.

20. The method of claim 19 wherein said circuit component comprises at least one of an oscillator and an inductor.

22. The method of claim 15 further comprising encapsulating a portion of said IC wafer in said molding material.

23. The method of claim 14 wherein said AGP layer comprises a glass frit.

25. The method of claim 18 wherein said conductive material comprises one of a conductive epoxy and a conductive epoxy paint.

26. The method of claim 18 further comprising arranging said layer of said conductive material on said AGP layer by dipping said IC package in a container containing said conductive material.