Barrier material and process for Cu interconnect

• US 20060113675A1
• Filed: 12/01/2004
• Published: 06/01/2006
• Est. Priority Date: 12/01/2004
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Chung-Liang, Shue, Shau-Lin, Hsieh, Ching-Hua
• Application Number:
  US11/001,471
• Publication Number:
  US 20060113675A1
• Time in Patent Office: Days
• US Class Current: 257/763
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal rich surface. Embodiments preferably include a glue layer about 10 to 500 Angstroms thick, the glue layer consisting of Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and a metal-rich nitride, and combinations thereof. The ratio of the glue layer thickness to the barrier layer thickness is preferably about 1 to 50. Other alternative preferred embodiments further include a conductor annealing step. The various layers may be deposited using PVD, CVD, PECVD, PEALD and/or ALD methods including nitridation and silicidation methods.

Claims

1. A semiconductor device having enhanced electromigration performance, the device comprising:

a low-k dielectric layer, the low-k dielectric layer having a surface with a recessed feature;

a diffusion barrier layer on the surface of the low-k dielectric layer;

a glue layer on the diffusion barrier layer; and

a conductor on the glue layer, the conductor filling the recessed feature.

2. The semiconductor device of claim 1, further including a cap layer on the conductor, wherein the cap layer is selected from the group consisting essentially of Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof.

3. The semiconductor device of claim 1, wherein the diffusion barrier layer includes a first barrier layer on the surface of the low-k dielectric layer and a second barrier layer on the first barrier layer.

4. The semiconductor device of claim 3, wherein the first barrier layer is selected from the group consisting essentially of Ta, W, and combinations thereof.

5. The semiconductor device of claim 3, wherein the second barrier layer is selected from the group consisting essentially of Ni, Co, Al, AlCu alloy, W, Ti, Ta, Ra, Ru, and combinations thereof.

6. The semiconductor device of claim 3, wherein the second barrier layer is selected from the group consisting essentially of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof.

7. The semiconductor device of claim 1, wherein the diffusion barrier layer is selected from the group consisting essentially of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof.

8. The semiconductor device of claim 7, wherein the diffusion barrier layer is metal rich.

9. The semiconductor device of claim 7, wherein the diffusion barrier layer further includes a metal rich surface.

10. The semiconductor device of claim 7, wherein the diffusion barrier layer further includes a thermal treatment to enhance adhesion.

11. The semiconductor device of claim 1, wherein the diffusion barrier layer is about 10 to 30 Angstroms.

12. The semiconductor device of claim 1, wherein the low-k dielectric layer comprises C, O, Si, and F.

13. The semiconductor device of claim 2, wherein the cap layer is selected from the group consisting essentially of a carbon-containing dielectric, a nitrogen-containing dielectric, a nitrogen-containing conductor, a silicon-containing conductive layer, and silicon, and combinations thereof.

14. The semiconductor device of claim 1, wherein the glue layer is selected from the group consisting essentially of a metal-rich nitride, Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and combinations thereof.

15. The semiconductor device of claim 14, wherein a thickness ratio of the glue layer to the diffusion barrier layer is about 1 to 50.

16. The semiconductor device of claim 14, wherein a thickness of the glue layer is about 10 to 500 Angstroms.

17. The semiconductor device of claim 14, wherein the metal-rich nitride comprises TaN and wherein an atomic ratio of nitrogen to tantalum is less than about 1.

18. The semiconductor device of claim 1, wherein the conductor is selected from the group consisting essentially of Cu, Al, Au, and Ag, and combinations thereof.

19. A method of reducing electromigration effects in a copper damascene device, the method comprising:

forming a low-k dielectric layer, the low-k dielectric layer having a surface with a recessed feature;

forming a diffusion barrier layer over the surface of the low-k dielectric layer;

forming a glue layer upon the diffusion barrier layer;

filing the recessed feature with a conductor;

annealing the conductor; and

forming a cap layer upon the conductor.

20. The method of claim 19, wherein the cap layer is selected from the group consisting essentially of Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof.

21. The method of claim 19, wherein the diffusion barrier layer is selected from the group consisting essentially of TaN, TiN, WN, ThN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof.

22. The method of claim 19, wherein the diffusion barrier layer is about 10 to 30 Angstroms.

23. The method of claim 19, wherein the cap layer is selected from the group consisting essentially of a carbon-containing dielectric, a nitrogen-containing dielectric, a nitrogen-containing conductor, a silicon-containing conductive layer, and silicon, and combinations thereof.

24. The method of claim 19, further including thermally treating the diffusion barrier layer.

25. The method of claim 19, wherein the glue layer is selected from the group consisting essentially of a metal-rich nitride, Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and combinations thereof.

26. The method of claim 25, wherein the glue layer is deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or plasma enhanced atomic layer deposition (PEALD).

27. The method of claim 25, wherein a thickness ratio of the glue layer to the diffusion barrier layer is about 1 to 50.

28. The method of claim 25, wherein a thickness of the glue layer is about 10 to 500 Angstroms.

29. The method claim 25, wherein the metal-rich nitride comprises TaN and wherein an atomic ratio of nitrogen to tantalum is less than about 1.

30. The method of claim 19, wherein the conductor annealing step comprises annealing at about 150 to 450°

C. for about 0.5 to 5 minutes in forming gas.

31. The method of claim 19, wherein the diffusion barrier layer is deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or plasma enhanced atomic layer deposition (PEALD).

32. The method of claim 19, wherein the cap layer is deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or plasma enhanced atomic layer deposition (PEALD).

33. A method for forming a semiconductor device, comprising:

providing a substrate, the substrate including a low-k dielectric layer with an opening;

performing a pore sealing process;

forming a barrier layer within the opening;

forming a glue layer on the barrier layer;

forming a seed layer on the glue layer;

forming a conductor on the seed layer;

and forming a cap layer on the conductor.

34. The method of claim 33, wherein the cap layer is selected from the group consisting essentially of Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof.

35. The method of claim 33, wherein the barrier layer is selected from the group consisting essentially of TaN, TiN, WN, ThN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof.

36. The method of claim 33, wherein the barrier layer is about 10 to 30 Angstroms.

37. The method of claim 33, wherein the cap layer is selected from the group consisting essentially of a carbon-containing dielectric, a nitrogen-containing dielectric, a nitrogen-containing conductor, a silicon-containing conductive layer, and silicon, and combinations thereof.

38. The method of claim 33, wherein the glue layer is selected from the group consisting essentially of a metal-rich nitride, Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and combinations thereof.

39. The method of claim 33, wherein a thickness ratio of the glue layer to the barrier layer is about 1 to 50.

40. The method of claim 33, wherein a thickness of the glue layer is about 10 to 500 Angstroms.

41. The method claim 38, wherein the metal-rich nitride comprises TaN and wherein an atomic ratio of nitrogen to tantalum is less than about 1.

42. The method of claim 33, further comprising annealing the conductor at about 150 to 450°

C. for about 0.5 to 5 minutes in forming gas.

43. The method of claim 33, wherein the pore sealing process comprises vapor pore sealing.