One time programmable latch and method

• US 20060114020A1
• Filed: 09/23/2005
• Published: 06/01/2006
• Est. Priority Date: 09/24/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Taheri, Babak, Maheshwari, Sanjeev
• Granted Patent: US 7,342,836 B2
• Time in Patent Office: Days
• US Class Current: 326/37
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 17/146 Write once memory, i.e. allowing changing of memory content by writing additional bits
• CPC Class Codes: G11C 17/16 using electrically-fusible links

Abstract

A one-time programmable (OTP) latch circuit can include a single OTP device capable of storing a logic value in a nonvolatile fashion, or only two OTP devices in the event redundancy is desired. A latch section can latch a data value based on a comparison between a current drawn according to the one OTP device, and a reference current generated without and OTP device. An OTP device can include a gate oxide antifuse (GOAF) device.

Claims

1. A programmable latch circuit, comprising:

a one-time programmable (OTP) device capable of being programmed only once to store a logic value;

a current source that provides a current reference not generated according to a state of any OTP device; and

a store circuit that stores a predetermined logic value based on a comparison between a current drawn in response to the OTP device and the reference current.

2. The programmable latch circuit of claim 1, wherein:

the OTP device comprises a gate oxide anti-fuse device.

3. The programmable latch circuit of claim 1, wherein:

the store circuit includes

a latch circuit that stores the predetermined logic value and includes at least two latch nodes that store complementary logic values,

a read out amplifier coupled to at least one of the latch nodes that amplifies the logic value thereon, and

pass device coupled to at least one of the latch nodes that provides a path for writing data to the latch circuit.

4. The programmable latch circuit of claim 1, wherein:

the current source is selected from the group consisting of;

a transistor pair that includes a first transistor in series with a second transistor, the first transistor being coupled to a power supply and the second transistor being enabled by a load signal that is active when a data value is loaded from the OTP device,

a transistor pair that includes a first transistor in series with a second transistor, the first transistor being coupled to a bias voltage at a level between power supply voltages, the second transistor being enabled by a load signal that is active when a data value is loaded from the OTP device,

a current mirror having a load transistor coupled in series with one of the current mirror legs, the load transistor being enabled by a load signal that is active when a data value is loaded from the OTP device,

a current mirror having load transistors coupled in series with both of the current mirror legs, the load transistors being enabled by a load signal that is active when a data value is loaded from the OTP device, and

a resistor in series with a load transistor, the load transistor being enabled by a load signal that is active when a data value is loaded from the OTP device control.

5. The programmable latch circuit of claim 1, further including:

the current source and a store circuit comprise insulated gate field effect transistors; and

an OTP circuit that includes the OTP device and at least a high voltage transistor, the high voltage transistor including a gate insulator that is more resistant to high voltage breakdown than the transistors of the current source and store circuit.

6. The programmable latch circuit of claim 5, wherein:

the store circuit includes a latch circuit that stores the predetermined logic value and includes at least two latch nodes that store complementary logic values; and

the OTP circuit includes the OTP device, the high voltage transistor, and a programming transistor, a source-drain path of the high voltage transistor being coupled between the OTP device and one of the latch nodes, a source-drain path of the programming transistor being coupled between the high voltage transistor and a low power supply voltage.

7. The programmable latch circuit of claim 1, further including:

a redundant OTP (R-OTP) device capable of being programmed only once to store a logic value, the R-OTP device being arranged in parallel with the OTP device, and not being programmed to match the state of the OTP device if the OTP device is not defective.

8. A one time programmable latch, comprising:

a latch circuit having cross-coupled data nodes that store a logic value;

a current source circuit coupled to a first data node that supplies a first current to a first data node in response to a load signal, the first current value not controlled according to any nonvolatile storage device; and

a one time programmable (OTP) device that draws essentially no current in a first state and a leakage current in the second state, the OTP device being coupled to a second data node in response to the load signal.

9. The one time programmable latch of claim 8, wherein:

the latch circuit comprises

a pair of latch transistors cross-coupled between the data nodes, and

a pair of hold transistors, a first hold transistor having a source-drain path coupled between a first data node and a first supply voltage, a second hold transistor having a source-drain path coupled between a second data node and the first supply voltage, the gate of the first and second hold transistors being commonly coupled to receive a hold signal.

10. The one time programmable latch of claim 9, wherein:

the latch circuit further includes

a pair of equalization transistor, a first equalization transistor having a source-drain path coupled between the first data node and a second supply voltage, a second equalization transistor having a source-drain path coupled between the second data node and the second supply voltage, the gate of the first and second equalization transistors being commonly coupled to receive an equalization signal.

11. The one time programmable latch of claim 8, further including:

a high voltage transistor having a source-drain path coupled between the OTP device and the second data node.

12. The one time programmable latch of claim 11, further including:

a programming transistor having a source-drain path coupled between the high voltage transistor and a second supply voltage, and gate coupled to one of the data nodes.

13. The one time programmable latch of claim 12, further including:

a program enable transistor having a source-drain path coupled between the gate of the programming transistor and the one of the data nodes.

14. The one time programmable latch of claim 8, further including:

an OTP load transistor having a source-drain path coupled between the OTP device and the second data node;

a current source load transistor having a source-drain path coupled between the current source circuit and the first data node;

wherein

the gates of the OTP load transistor and current source load transistor are commonly coupled to receive a load signal.

15. A method of programmable latching, comprising the steps of:

establishing a state of a one time programmable (OTP) device to provide a programmed current value representing a predetermined logic value;

providing a reference current that is not generated from an OTP device; and

latching a data value based on a difference between the programmed current and the reference current.

16. The method of programmable latching of claim 15, wherein:

establishing the state of the OTP device includes,

to store one logic value, creating a short in an insulator of a gate oxide antifuse device that draws a leakage current, and

to store another logic value, not altering the gate insulator of the gate oxide antifuse device to draw essentially no current with the gate oxide antifuse device.

17. The method of programmable latching of claim 16, wherein:

the reference current is less than the leakage current.

18. The method of programmable latching of claim 15, wherein:

providing the reference current includes biasing a current supply transistor.

19. The method of programmable latching of claim 15, further including:

when programming one state of the OTP device,

writing one data value to a latch, and

enabling a programming potential to the OTP device when the latch stores a particular data value.

20. The method of programmable latching of claim 15, wherein:

providing the reference current includes generating the reference current from a digital value.