Methods and apparatuses for changing capacitance

• US 20060114072A1
• Filed: 11/30/2005
• Published: 06/01/2006
• Est. Priority Date: 11/30/2004
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Hwi-taek, Lee, Seung-won, Lee, Byeong-hoon
• Application Number:
  US11/289,286
• Publication Number:
  US 20060114072A1
• Time in Patent Office: Days
• US Class Current: 331/57
• CPC Class Codes: H03K 17/00 Electronic switching or gating, i.e. not by contact-making and –breaking gated amplifiers H03F3/72; switching arrangements for exchange systems using static devices H04Q3/52
• CPC Class Codes: H03K 3/00 Circuits for generating electric pulses; Monostable, bistable or multistable circuits H03K4/00 takes precedence; for digital function generators in computers G06F1/02
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

Methods and apparatuses for changing capacitance are provided. The apparatus may adjust a current supplied to a load capacitor according to the frequency of an input clock signal. When operating at a lower frequency, a capacitance may be increased such that noise immunity may be increased. When operating at a higher frequency, a capacitance may be decreased such that current consumption may be reduced.

Claims

1. An oscillator comprising:

a plurality of amplifiers generating an oscillation signal having a resonance frequency according to a control voltage and variations in inductance and capacitance, and outputting the oscillation signal; and

a plurality of load capacitors having variable capacitances corresponding to an initial frequency range of an input signal.

2. The oscillator of claim 1, wherein each of the load capacitors further includes,

a plurality of capacitors having different capacitances and connected in parallel, and

a plurality of switches each of which is connected between one of the plurality of capacitors and a ground voltage, and which is turned on or off according to the initial frequency range of the input signal.

3. The oscillator of claim 1, wherein the capacitance of each of the load capacitors increases as the frequency of the input clock signal enters a lower frequency range.

4. The oscillator of claim 2, wherein the frequency band of the input signal is divided into N frequency ranges, and the plurality of switches includes N switches each of which corresponds to a respective one of the frequency ranges or log₂(N) switches corresponding to combinations of the N frequency ranges.

5. The oscillator of claim 4, wherein the capacitance of the load capacitor is increased by closing one of the switches connected to one of the capacitor with a lower capacitance as the frequency of the input clock signal enters a lower frequency band.

6. The oscillator of claim 4, wherein the switch corresponding to frequency range is not toggled when the frequency of the input signal enters a frequency range adjacent to the initial frequency range.

7. The oscillator of claim 6, wherein the capacitance of the load capacitor is increased by closing one of the switches connected to one of the capacitor with a lower capacitance as the input clock signal enters a lower frequency band.

8. The oscillator of claim 1, further including,

a plurality of inductors each connected in parallel with a respective load capacitor and generating an inductance;

and

a plurality of resistors connected in parallel with one of the respective load capacitors and generating a resistance.

23. An apparatus including the oscillator of claim 1.

9. An apparatus comprising:

a phase detector comparing the phase of an input clock signal with the phase of a fed-back output clock signal and outputting a result of comparison;

a charge pump outputting a control voltage based on the output of the phase detector;

a voltage controlled oscillator generating an oscillation signal having a frequency corresponding to the control voltage output from the charge pump and outputting the oscillation signal as a clock signal;

a frequency divider dividing the clock signal output from the voltage controlled oscillator and feeding back the divided clock signal to the phase detector; and

a frequency range detector dividing a frequency band of the input clock signal into a plurality of frequency ranges and outputting a frequency range detection signal corresponding to the initial frequency range of the input signal, wherein

the voltage controlled oscillator includes a plurality of load capacitors providing a variable capacitance corresponding to the frequency range detection signal.

10. The apparatus of claim 9, wherein the voltage controlled oscillator including a plurality of amplifiers generating the oscillation signal having a resonance frequency according to an input control voltage and changes in inductance and capacitance, and outputting the oscillation signal.

11. The apparatus of claim 10, wherein each of the load capacitors includes,

a plurality of capacitors having different capacitances connected in parallel to one another;

and

a plurality of switches each of which is connected between a respective capacitor and a ground voltage, and turned on or off according to the frequency range of the inputted signal.

12. The apparatus of claim 10, wherein the capacitance of each of the load capacitors increases as the frequency of the detection signal output from the frequency range detector enters a lower frequency range.

13. The apparatus of claim 11, wherein the frequency band of the inputted signal is divided into N frequency ranges, and the plurality of switches includes N switches corresponding to each of the frequency ranges or log₂(N) switches corresponding to combinations of the N frequency ranges.

14. The apparatus of claim 13, wherein as a lower frequency band of the input clock signal is input to a switch connected to the capacitor having a higher capacitance, and as a higher frequency band of the input clock signal is input to a switch connected to the capacitor having a lower capacitance.

15. The apparatus of claim 13, wherein the switch corresponding to the initial frequency range of the input signal is not toggled when the frequency of the input signal enters an adjacent frequency range.

16. The apparatus of claim 15, wherein as a lower frequency band of the input clock signal is input to a switch connected to the capacitor having a higher capacitance, and as a higher frequency band of the input clock signal is input to a switch connected to the capacitor having a lower capacitance.

17. The apparatus of claim 9, wherein the voltage controlled oscillator further includes,

each of a plurality of inductors connected in parallel with a respective one of the load capacitors and generating an inductance, and

each of a plurality of resistors connected in parallel with a respective one of the load capacitors and generating a resistance.

18. A decoder comprising:

a plurality of logic circuits each having at least two inputs and one output; and

each activating a respective frequency detection signal in response to receiving at least two frequency signals or at least two frequency signals and at least one frequency detection signal.

21. A detector including the decoder of claim 18.

22. An apparatus including the detector of claim 21.

19. A detector comprising:

a plurality of delay units each delaying a clock signal;

a plurality of logic units, each receiving the clock signal and a delayed clock signal, and each outputting a respective output signal based on the received clock signal and delayed clock signal, each of the delayed clock signals being output from a respective one of the plurality of delay units; and

a decoder receiving each output signal and outputting a frequency selection signal indicative of a selected frequency range based on the received output signals.

20. A method comprising:

comparing a phase of an input clock signal with the phase of a fed-back output clock signal and outputting a result of comparison;

outputting a control voltage based on the output result;

generating an oscillation signal having a frequency corresponding to the output control voltage and outputting the oscillation signal as a clock signal;

dividing the output clock signal to generate the fed-back output clock signal; and

dividing a frequency band of the input clock signal into a plurality of frequency ranges and outputting a frequency range detection signal corresponding to the initial frequency range of the input signal, wherein

the oscillation signal is generated using a variable capacitance corresponding to the frequency range detection signal.

24. An apparatus for performing the method of claim 20.