Nonvolatile semiconductor memory cell and method of manufacturing the same

• US 20060114736A1
• Filed: 01/13/2006
• Published: 06/01/2006
• Est. Priority Date: 01/05/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozawa, Yoshio
• Granted Patent: US 7,312,498 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence

Abstract

A stacked-gate structure includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on a semiconductor substrate. The inter-electrode insulation film has a three-layer structure that includes a first oxidant barrier layer, an intermediate insulation layer and a second oxidant barrier layer. Gate side-wall insulation films are formed on both side surfaces of the stacked-gate structure. The thickness of the gate side-wall insulation film increases, at a side portion of the floating gate electrode, from the inter-electrode insulation film side toward the tunnel insulation film side. The width of the floating gate electrode in a channel length direction decreases from the inter-electrode insulation film side toward the tunnel insulation film side.

Claims

1-11. -11. (canceled)

12. A method of manufacturing a nonvolatile semiconductor memory cell, comprising:

forming a tunnel insulation film on a semiconductor substrate;

forming on the tunnel insulation film a first conductive layer that becomes a floating gate electrode;

forming on the first conductive layer an inter-electrode insulation film that includes a first oxidant barrier layer, which suppresses passage of oxidant, an intermediate insulation layer, and a second oxidant barrier layer, which suppresses passage of oxidant;

forming on the inter-electrode insulation film a second conductive layer that becomes a control gate electrode;

forming a stacked-gate structure by selectively etching the first conductive layer, the second conductive layer and the inter-electrode insulation film; and

forming gate side-wall insulation films on side parts of the floating gate electrode by oxidizing or oxynitriding side surfaces of the stacked-gate structure, each of the gate side-wall insulation films having a thickness increasing from the inter-electrode insulation film side toward the tunnel insulation film side.

13. The method according to claim 12, wherein a third oxidant barrier layer is formed on the second conductive layer, prior to formation of the gate side-wall insulation films.

14. The method according to claim 12, wherein a third oxidant barrier layer is formed on the second conductive layer, prior to formation of the gate side-wall insulation films, and oxidation or oxynitridation is performed to form the gate side-wall insulation films in a state in which the third oxidant barrier layer is present on the second conductive layer.

15. The method according to claim 14, wherein the third oxidant barrier layer is removed after formation of the gate side-wall insulation films, and a third conductive layer having a lower resistance than the second conductive layer is formed on the second conductive layer.

16. The method according to claim 12, wherein after formation of the gate side-wall insulation films, source/drain diffusion layers are formed by implanting dopant ions in the semiconductor substrate, using the gate side-wall insulation films as a mask.

17. The method according to claim 12, wherein the inter-electrode insulation film has as substantially flat structure, and an area of the tunnel insulation film, which contacts the floating gate electrode, is 70% or less of an area of the inter-electrode insulation film, which contacts the floating gate electrode.

18. The method according to claim 12, wherein the conductive layers are thermally oxidized by RTP (Rapid Thermal Process), thereby to form the gate side-wall insulation films.

19. A method of manufacturing a nonvolatile semiconductor memory cell, comprising:

forming a tunnel insulation film on a semiconductor substrate;

forming on the tunnel insulation film a first conductive layer that becomes a floating gate electrode;

forming on the first conductive layer an inter-electrode insulation film that includes a first oxidant barrier layer, which suppresses passage of oxidant, an intermediate insulation layer, and a second oxidant barrier layer, which suppresses passage of oxidant;

forming on the inter-electrode insulation film a second conductive layer that becomes a control gate electrode lower-layer;

forming a third oxidant barrier layer on the second conductive layer;

forming a stacked-gate structure by selectively etching the first conductive layer, the second conductive layer, the inter-electrode insulation film and the third oxidant barrier layer;

forming first gate side-wall insulation films on side parts of the floating gate electrode and second gate side-wall insulation films on side parts of the control gate electrode lower-layer by oxidizing or oxynitriding side surfaces of the stacked-gate structure, each of the first gate side-wall insulation films having a thickness increasing from the inter-electrode insulation film side toward the tunnel insulation film side, and each of the second gate side-wall insulation films having a thickness decreasing from a central part thereof toward the oxidant barrier layers; and

removing the third oxidant barrier layer and then forming on the control gate electrode lower-layer a control gate electrode upper-layer that has a lower resistance than the control gate electrode lower-layer.

20. (canceled)