CPU transmission of unmodified packets

• US 20060114895A1
• Filed: 03/28/2005
• Published: 06/01/2006
• Est. Priority Date: 11/30/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Anand, Anupam, Dull, John Jeffrey
• Granted Patent: US 8,170,019 B2
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3063 Pipelined operation

Abstract

A network device for processing packet. The network device includes an ingress module for performing switching functionality on an incoming packet, wherein the network device determines a destination port to which the incoming packet is to be transmitted. The network device also includes a CPU processing module for transmitting information between the network device and an external CPU. The external CPU transmits a formatted packet to the network device through the CPU processing module. The formatted packet includes module header and a data field. The ingress module uses information in a start field of the module header to determine that the incoming packet is a formatted packet and generates instructions for notifying other modules of the network device that the formatted packet is not to be modified by the network device and determines that the formatted packet is to be transmitted to a destination field in the formatted packet.

Claims

1. A network device for processing packets, the network device comprising:

an ingress module for performing switching functionality on an incoming packet, wherein the network determines a destination port to which the incoming packet is to be transmitted; and

a CPU processing module for transmitting information between the network device and an external CPU, wherein the external CPU transmits a formatted packet to the network device through the CPU processing module, the formatted packet includes a module header and a data field,

wherein the ingress module uses information in a start field of the module header to determine that the incoming packet is a formatted packet and generates instructions for notifying other modules of the network device that the formatted packet is not to be modified by the network device and determines that the formatted packet is to be transmitted to a destination field in the formatted packet.

2. The network device of claim 1, wherein the CPU processing module is configured to receive the module header comprising a field for indicating a local destination port.

3. The network device of claim 1, wherein the CPU processing module to a destination port to which the packet is being transmitted.

4. The network device of claim 1, wherein the CPU processing module is configured to receive the data field comprising a final module header and packet information when the formatted packet is being transmitted to a high speed port.

5. The network device of claim 1, further comprising a 32-bit wide bus between the CPU processing module and ingress module in three cycles, wherein the formatted packet is transmitted on the 32-bit wide bus.

6. The network device of claim 1, wherein the ingress module comprises an arbiter that is configured to schedule request from the CPU processing module and wherein when the incoming packet is identified as a formatted packet, the arbiter generates an instruction that indicates that the formatted packet should not be modified by the network device.

7. The network device of claim 6, wherein the arbiter is configure to transmit an unmodified module header and the data field through a ingress pipeline over an overlay bus and a packet data bus.

8. The network device of claim 1, wherein the ingress module comprises a switching stage that this configured to receive the data field, the switching stage is further configured to construct PBI fields and transmit the PBI field with the data field to other modules of the network device.

9. The network device of claim 1, wherein a memory management unit is configured to apply resource accounting and aging logic to the formatted packet.

10. The network device of claim 1, an egress module is configured to construct a pipeline command for the formatted and transmit the data field to a packet buffer, wherein all table lookups and switching decisions are skipped in the egress module and the egress module transmits the data field to at least one appropriate destination port identified by the formatted packet.

11. A method for processing packets in a network device, the method comprises the steps of:

receiving an incoming packet from an external CPU, wherein the incoming packet includes a module header and a data field;

using information in a start field of the module header to determine that the incoming packet is a formatted packet;

generating instructions for notifying modules of the network device that the formatted packet is not to be modified by the network device; and

determining a destination port to which the formatted packet is to be transmitted based on a destination field in the formatted packet.

12. The method of claim 11, further comprising including a final module header and packet information when the formatted packet is being transmitted to a high speed port.

13. The method of claim 11, further comprising transmitting the formatted packet on a 32-bit wide bus between an CPU processing module and a ingress module in three cycles.

14. The method of claim 11, further comprising generating an instruction that indicates that the formatted packet should not be modified by the switching chip when the incoming packet is identified as a formatted packet.

15. The method of claim 11, further comprising transmitting an unmodified module header and data field through an ingress pipeline over an overlay bus and a packet data bus.

16. The method of claim 11, further comprising constructing PBI fields in a switching stage and passing the PBI field with the data field to other modules of the switching chip.

17. The method of claim 11, further comprising applying resource accounting and aging logic to the formatted packet.

18. The method of claim 11, further comprising constructing a pipeline command for the formatted and passing the data field to a packet buffer, wherein all table lookups and switching decisions are skipped in an egress module and the egress module transmits the data field to at least one appropriate destination port identified by the formatted packet.

19. An apparatus for processing a packet in a network device, the apparatus includes:

receiving means for receiving an incoming packet from an external CPU, wherein the incoming packet includes a module header and a data field;

using means for using information in a start field of the module header to determine that the incoming packet is a formatted packet;

generating means for generating instructions for notifying modules of the switching chip that the formatted packet is not to be modified by the switching chip; and

determining for determining a destination port to which the formatted packet is to be transmitted based on a destination field in the formatted packet.