Method of making a microelectromechanical (MEM) device using porous material as a sacrificial layer

• US 20060115919A1
• Filed: 11/30/2004
• Published: 06/01/2006
• Est. Priority Date: 11/30/2004
• Status: Abandoned Application

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Gogoi, Bishnu P., Zheng, Jin
• Application Number:
  US11/000,547
• Publication Number:
  US 20060115919A1
• Time in Patent Office: Days
• US Class Current: 438/50
• CPC Class Codes: B81B 2203/0109 Bridges
• CPC Class Codes: B81B 2203/0118 Cantilevers
• CPC Class Codes: B81C 1/00476 removing a sacrificial layer B81C1/00912 takes precedence
• CPC Class Codes: B81C 2201/0109 Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
• CPC Class Codes: B81C 2201/0115 Porous silicon
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 2015/0814 for translational movement of the mass, e.g. shuttle type

Abstract

A method of making a microelectromechanical (MEM) device using a standard silicon wafer, rather than an SOI wafer, includes selectively implanting a dopant in regions of the standard wafer, to thereby form heavily doped regions therein. The heavily doped regions are then converted to porous silicon regions. An electrical isolation layer is selectively deposited on the wafer and over a portion of one or more of the porous silicon regions. An epitaxial layer is grown over the porous silicon regions and the electrical isolation area, and device elements are formed in the epitaxial layer. Thereafter, at least portions of the porous silicon regions are removed, to thereby release the formed device elements.

Claims

1. A method of forming a device on a substrate, comprising the steps of:

selectively doping one or more regions of the substrate with a dopant of the first conductivity type, to thereby form one or more heavily doped regions;

selectively forming one or more electrical isolation regions on at least selected regions of the substrate;

converting the heavily doped regions to porous silicon regions;

growing an epitaxial silicon layer over the porous silicon regions and the one or more electrical isolation regions;

forming device elements in the epitaxial silicon layer; and

removing at least a portion of the porous silicon regions to thereby release at least some of the formed device elements.

2. The method of claim 1, further comprising:

driving the selectively implanted dopant to form the heavily doped regions.

3. The method of claim 2, wherein the implanted dopant is driven into the heavily doped regions using a thermal process.

4. The method of claim 1, wherein the dopant is n-type dopant.

5. The method of claim 1, wherein the heavily doped regions are converted to the porous silicon regions using an electrochemical etch process.

6. The method of claim 1, wherein the porous silicon regions include pores having a predetermined size, the predetermined pore size being sufficient to allow the epitaxial silicon layer to grow thereon.

7. The method of claim 6, wherein the predetermined pore size in the range of from about 1 nm to about 20 nm.

8. The method of claim 1, further comprising:

after selectively doping regions of the substrate with the dopant, thermally driving the dopant into the heavily doped regions.

9. The method of claim 1, further comprising:

depositing a layer of an electrical isolation material; and

patterning and etching the deposited layer of electrical isolation material to form the one or more electrical isolation regions.

10. The method of claim 9, further comprising:

applying a mask layer over at least the porous silicon regions at least prior to etching the deposited electrical isolation material layer.

11. The method of claim 1, wherein the one or more electrical isolation regions each comprise silicon nitride.

12. The method of claim 1, wherein the one or more electrical isolation regions each comprise low stress silicon rich silicon nitride.

13. The method of claim 1, wherein the one or more electrical isolation regions are sized to allow growth of the epitaxial silcon layer thereon.

14. The method of claim 1, wherein the device that is formed is a microelectromechanical (MEM) device.

15. The method of claim 1, wherein the porous silicon regions are at least partially removed using either tetramethyl ammonium hydroxide (TMAH) or potassium hydroxide (KOH).

16. The method of claim 1, further comprising:

lightly doping the substrate with the dopant of the first conductivity type, to thereby form a lightly doped substrate,

wherein the one or more heavily doped regions are formed in the lighly doped substrate.

17. The method of claim 1, wherein the substrate comprises a single crystal material.

18. The method of claim 1, wherein the substrate comprises single crystal silicon.

19. A method of forming a device on a lightly doped substrate, the substrate lightly doped with a dopant of a first conductivity type, the method comprising the steps of:

selectively doping regions of the lightly doped substrate with the dopant of the first conductivity type, to thereby form heavily doped regions;

selectively forming one or more electrical isolation regions on at least selected regions of the lightly doped substrate;

converting the heavily doped regions to porous silicon regions;

growing an epitaxial layer over the porous silicon regions and each deposited electrical isolation area;

forming device elements in the epitaxial layer; and

removing at least a portion of the porous silicon regions to thereby release at least a portion of the formed device elements.

20. The method of claim 19, further comprising:

driving the selectively implanted dopant to form the heavily doped regions.

21. The method of claim 20, wherein the implanted dopant is driven into the heavily doped regions using a thermal process.

22. The method of claim 19, wherein the dopant is n-type dopant.

23. The method of claim 19, wherein the heavily doped regions are converted to the porous silicon regions using an electrochemical etch process.

24. The method of claim 19, wherein the porous silicon regions include pores having a predetermined size, the predetermined pore size being sufficient to allow the epitaxial silicon layer to grow thereon.

25. The method of claim 24, wherein the predetermined pore size in the range of from about 1 nm to about 20 nm.

26. The method of claim 19, further comprising:

after selectively doping regions of the lightly doped substrate with the dopant, thermally driving the dopant into the heavily doped regions.

27. The method of claim 19, further comprising:

depositing a layer of an electrical isolation material; and

patterning and etching the deposited electrical isolation material layer to form the electrical isolation regions.

28. The method of claim 27, further comprising:

applying a mask layer over at least the porous silicon regions at least prior to etching the deposited electrical isolation material layer.

29. The method of claim 19, wherein the electrical isolation regions each comprise silicon nitride.

30. The method of claim 19, wherein the electrical isolation regions each comprise low stress silicon rich silicon nitride.

31. The method of claim 19, wherein the electrical isolation regions are sized to allow growth of the epitaxial silicon layer thereon.

32. The method of claim 19, wherein the device that is formed is a microelectromechanical (MEM) device.

33. The method of claim 19, wherein the porous silicon regions are at least partially removed using either tetramethyl ammonium hydroxide (TMAH) or potassium hydroxide (KOH).

34. The method of claim 19, wherein the substrate comprises a single crystal material.

35. The method of claim 19, wherein the substrate comprises single crystal silicon.