Method for forming an improved T-shaped gate structure

• US 20060115938A1
• Filed: 11/30/2004
• Published: 06/01/2006
• Est. Priority Date: 11/30/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chu, Wen-Ting, Wu, Chung-Cheng
• Granted Patent: US 7,749,911 B2
• Time in Patent Office: Days
• US Class Current: 438/182
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence

Abstract

A T-shaped gate structure and method for forming the same the method including providing a semiconductor substrate comprising at least one overlying sacrificial layer; lithographically patterning a resist layer overlying the at least one sacrificial layer for etching an opening; forming the etched opening through a thickness of the at least one sacrificial layer to expose the semiconductor substrate, said etched opening comprising a tapered cross section having a wider upper portion compared to a bottom portion; and, backfilling the etched opening with a gate electrode material to form a gate structure.

Claims

1. A method of forming a T-shaped gate structure comprising the steps of:

providing a semiconductor substrate comprising at least one overlying sacrificial layer;

forming an opening through a thickness of the at least one sacrificial layer to expose the semiconductor substrate, said opening comprising a tapered cross section having a wider upper portion compared to a bottom portion; and

,

backfilling the opening with a gate electrode material to form a gate structure.

2. The method of claim 1, wherein the step of backfilling comprises a CMP process to remove the gate electrode material overlying the at least one sacrificial layer.

3. The method of claim 1, further comprising the step of carrying out an ion implant process to form source and drain regions adjacent the gate structure substantially aligned with an uppermost portion of the gate structure.

4. The method of claim 1, wherein an upper portion of the etched opening comprises a first sidewall taper angle and the bottom portion of the etched opening comprises a second sidewall taper angle closer to vertical compared to the first sidewall taper angle.

5. The method of claim 1, wherein the at least one sacrificial layer comprises a silicon oxide layer on the semiconductor substrate and a nitride layer on the silicon oxide layer.

6. The method of claim 5, wherein the nitride layer is selected from the group consisting of silicon nitride and silicon oxynitride.

7. The method of claim 5, wherein the step of forming the etched opening comprises a dry etching process to etch through the nitride layer.

8. The method of claim 5, wherein the step of forming the etched opening comprises a wet etching process to etch through the silicon oxide layer.

9. The method of claim 7, wherein the dry etching process comprises an etching chemistry with a fluorine to carbon ratio greater than about 2.5.

10. The method of claim 7, wherein the dry etching chemistry comprises hexafluoroethane (C₂F₆).

11. The method of claim 10, wherein the dry etching chemistry comprises argon.

12. The method of claim 7, wherein the dry etching process comprises cooling the process surface to between about 0°

and about 20°

C.

13. The method of claim 1, further comprising the step of forming a gate dielectric material at the bottom of the etched opening prior to the step of backfilling.

14. The method of claim 13, wherein the gate dielectric is thermally grown on the semiconductor substrate.

15. The method of claim 1, further comprising the step of removing the at least one sacrificial layer following the step of backfilling.

16. The method of claim 1, wherein the gate electrode material is selected from the group consisting of polysilicon, amorphous polysilicon, doped polysilicon and poly-silicon-germanium.

17. The method of claim 1, wherein the gate electrode material comprises a material selected from the group consisting of metals, metal oxides, and metal nitrides.

18. A method of forming a T-shaped gate structure comprising the steps of:

providing a semiconductor substrate comprising an overlying silicon oxide layer and a nitride layer overlying the silicon oxide layer;

lithographically patterning a resist layer overlying the nitride layer for etching an opening;

forming the etched opening through a thickness of the nitride and silicon oxide layers to expose the semiconductor substrate, said etched opening comprising a tapered cross section having a wider upper portion compared to a bottom portion;

backfilling the etched opening with a gate dielectric on the semiconductor substrate and a gate electrode material on the gate dielectric;

removing at least the nitride layer to form a gate structure; and

,

carrying out an ion implant process to form source and drain regions substantially aligned with the upper portion of the gate structure.

19. A T-shaped gate structure comprising:

a gate dielectric on a semiconductor substrate;

a gate electrode on the gate dielectric;

wherein the gate electrode comprises a tapered cross section having a wider upper portion compared to a bottom portion.

20. The T-shaped gate structure claim 19, wherein the upper portion of the gate electrode comprises a first sidewall taper angle and the bottom portion of the gate electrode comprises a second sidewall taper angle closer to vertical compared to the first sidewall taper angle.

21. The T-shaped gate structure claim 19, further comprising source and drain regions in the semiconductor substrate substantially aligned with the upper portion of the gate electrode.

22. The T-shaped gate structure claim 19, wherein the gate electrode comprises a material selected from the group consisting of polysilicon, amorphous polysilicon, doped polysilicon and poly-silicon-germanium.

23. The T-shaped gate structure claim 19, wherein the gate electrode comprises a material selected from the group consisting of metals, metal oxides, and metal nitrides.

24. A T-shaped gate structure comprising:

a gate dielectric on a semiconductor substrate;

a gate electrode on the gate dielectric;

wherein the gate electrode comprises a tapered cross section having a wider upper portion compared to a bottom portion; and

,

source and drain regions in the semiconductor substrate substantially aligned with the upper portion of the gate electrode.