Capacitor having an anodic metal oxide substrate

• US 20060115951A1
• Filed: 01/06/2006
• Published: 06/01/2006
• Est. Priority Date: 12/23/2003
• Status: Active Grant

• Current Assignee: Larry E. Mosley
• Original Assignee: Larry E. Mosley
• Inventors: Mosley, Larry E.
• Granted Patent: US 7,288,460 B2
• Time in Patent Office: Days
• US Class Current: 438/381
• CPC Class Codes: H01G 4/10 Metal-oxide dielectrics H01G4/085 takes precedence
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19103 interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19106 in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/932 for electronic or optoelectronic application

Abstract

A structure and method including an anodic metal oxide substrate used to form a capacitor are described herein.

Claims

1. A method of forming a capacitor, comprising:

anodizing at least a portion of a metal plate to form a plurality of nanopores and an insulating oxide layer; and

depositing a conductive material in the plurality of nanopores to produce a plurality of nanowires electrically isolated from the metal plate by the insulating oxide layer.

2. The method according to claim 1, further comprising:

forming a first electric connection to the metal plate; and

forming a second electrical connection to the plurality of nanowires.

3. The method according to claim 2, wherein anodizing at least the portion of the metal plate further includes anodizing at least one side of the metal plate and wherein depositing the conductive material further includes depositing the conductive material on the oxide layer of the one side to form the nanowires in the nanopores and to electrically interconnect the nanowires formed in the one side.

4. The method according to claim 2, wherein anodizing at least the portion of the metal plate further includes anodizing a pair of opposed sides of the metal plate and depositing the conductive material further includes depositing the conductive material on the pair of opposed sides.

5. The method according to claim 2, further comprising:

prior to anodizing the metal plate, depositing a plurality of spaced-apart protective coatings on the portion of the metal plate;

after depositing the conductive material, forming the first electric connection with the metal plate further includes opening the protective coatings to form a plurality of first terminals on the metal plate; and

after depositing the conductive material, forming the second electrical connection with the plurality of nanowires further includes forming a plurality of second terminals on the conductive layer.

6. The method according to claim 5, wherein depositing the plurality of protective coatings includes uniformly distributing the protective coatings on the portion of the metal plate.

7. The method according to claim 5, wherein the plurality of first terminals comprises a plurality of power supply terminals and the plurality of second terminals comprises a plurality of ground terminals.

8. The method according to claim 5, wherein forming the first and second electrical connections further includes positioning the first terminals and second terminals in an alternating repetitive pattern.

9. The method according to claim 4, further comprising:

prior to anodizing the metal plate, depositing a plurality of spaced-apart protective coatings on the pair of opposed sides of the metal plate;

after depositing the conductive material, forming the first electric connection with the metal plate further includes opening the protective coatings to form a plurality of first terminals on the metal plate; and

after depositing the conductive material, forming the second electrical connection with the plurality of nanowires further includes forming a plurality of second terminals on the conductive layer.

10. The method according to claim 9, wherein the plurality of first terminals comprises a plurality of power supply terminals and the plurality of second terminals comprises a plurality of ground terminals.

11. The method according to claim 10, further comprising:

forming a plurality of holes in the metal plate; and

depositing a plurality of conductors in the plurality of holes for input/output signals.