Network processor system

• US 20060117088A1
• Filed: 01/10/2006
• Published: 06/01/2006
• Est. Priority Date: 12/22/1999
• Status: Active Grant

• Current Assignee: Brian A. Petersen, Mark A. Ross
• Original Assignee: Brian A. Petersen, Mark A. Ross
• Inventors: Ross, Mark A., Petersen, Brian A.
• Granted Patent: US 7,860,967 B2
• Time in Patent Office: Days
• US Class Current: 709/206
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: Y10S 707/99933 Query processing, i.e. searching

Abstract

The present invention consists of a general purpose, software-controlled central processor (CP) augmented by a set of task specific, specialized peripheral processors (PPs). The central processor accomplishes its functions with the support of the PPs. Peripheral processors may include but are not limited to a packet parser, which provides the central processor with a numerical summary of the packet format; a packet deconstructor, which extracts designated fields from the packet the positions of which are determined by the central processor according to the packet format; a search engine, which is supplied a lookup index by and returns its results to the central processor; and a packet editor which modifies the packet as determined by the central processor using (in part) information returned from other peripherals. At each step in the use of this network processor system, the central processor has an opportunity to intervene and modify the handling of the packet based on its interpretation of PP results. The programmable nature of the CP and the PPs provides the system with flexibility and adaptability: rather than having to modify a circuit or system design in an ASIC or other hardware, new packet processing applications may be accommodated through the development of new software and its deployment in the central and/or peripheral processors.

Claims

1-29. -29. (canceled)

30. An apparatus comprising:

a peripheral processor, wherein

said peripheral processor is configured to perform a packet processing task; and

a central processor, wherein

said central processor is coupled to control said peripheral processor,

said central processor is configured to cause said peripheral processor to perform said packet processing task, and

said central processor and said peripheral processor are configured to communicate with one another

31. The apparatus of claim 30, wherein

said packet processing task is one of a plurality of packet processing tasks, and

said peripheral processor is configured to perform a plurality of said packet processing tasks.

32. The apparatus of claim 30, further comprising:

a plurality of peripheral processors, wherein

said peripheral processors comprise said peripheral processor,

said packet processing task is one of a plurality of packet processing tasks, and

each of said peripheral processors is configured to perform at least one of said packet processing tasks.

33. The apparatus of claim 32, wherein

said central processor and said peripheral processors are configured to perform said packet processing tasks in one of sequentially and parallel.

34. The apparatus of claim 32, wherein

said central processor is configured to receive a packet,

said central processor is coupled to control said peripheral processors,

said central processor is configured to cause said peripheral processors to perform at least one of said at least one of said packet processing tasks, and

said central processor and said peripheral processors are configured to communicate with one another.

35. The apparatus of claim 34, wherein

said peripheral processors comprise at least one of a packet parsing processor, a packet deconstruction processor, a search engine processor and a packet editing processor.

36. The apparatus of claim 35, wherein

said packet editing processor is configured to modify routing information in a header of said packet using information provided by at least one of said packet parsing processor, said packet deconstruction processor and said search engine processor.

37. The apparatus of claim 34, wherein

said peripheral processors comprise a packet parsing processor, and

said packet parsing processor is configured to generate a numerical summary of said packet.

38. The apparatus of claim 37, wherein

said central processor is further configured to cause said packet parsing processor to perform said generating, and

said packet parsing processor is configured to provide said numerical summary to said central processor.

39. The apparatus of claim 34, wherein

said peripheral processors comprise a packet deconstruction processor, and

said packet deconstruction processor is configured to extract a field from said packet.

40. The apparatus of claim 39, wherein

said central processor is further configured to designate said field to communicate said designation to said packet deconstruction processor.

41. The apparatus of claim 34, wherein

said peripheral processors comprise a search engine processor, and

said search engine processor is configured to identify network information associated with said packet.

42. The apparatus of claim 41, wherein

said search engine processor is configured to perform said identification by virtue of being configured to determine routing information by virtue of being configured to perform a lookup operation in a routing information table.

43. The apparatus of claim 34, wherein

said peripheral processors comprise a packet editing processor, and

said packet editing processor is configured to modify information in said packet.

44. The apparatus of claim 43, wherein

said packet editing processor is configured to perform said modification by virtue of being configured to modify routing information in a header of said packet.

45. A method comprising:

receiving a packet;

determining a vector by parsing at least a portion of said packet; and

processing said packet by performing a plurality of packet processing tasks, wherein

said processing comprises causing a central processor to coordinate said packet processing tasks using said vector,

said coordinating comprises causing a peripheral processor to perform at least one of said packet processing tasks, and

said central processor is coupled to cause said peripheral processor to perform said at least one of said packet processing tasks.

46. The method of claim 45, wherein said peripheral processor is one of a plurality of peripheral processors, and said packet processing tasks comprise at least one of:

deconstructing said packet header to form header data;

searching one or more data structures based on said header data to produce search results; and

editing said packet based on said search results, said header data, and said vector, wherein each of said deconstructing, said searching and said editing are performed by a corresponding one of said peripheral processors.

47. The method of claim 46, wherein said coordinating further comprises:

monitoring said deconstructing, said searching, and said editing, and

causing said peripheral processors to share information regarding said packet among one another.

48. The method of claim 46, wherein:

said deconstructing further comprises forming a search argument;

said coordinating further comprises operating on said search argument to form a modified search argument prior to said searching; and

said searching uses said modified search argument.

49. An apparatus comprising:

a peripheral processor;

a central processor, coupled to control said peripheral processor and configured to receive a packet;

means for determining a vector comprising means for parsing at least a portion of said packet; and

means for processing said packet comprising means for performing a plurality of packet processing tasks, wherein

one of said means for performing said processing tasks comprises said peripheral processor,

said means for processing comprises means for causing said central processor to coordinate said packet processing tasks using said vector,

means for causing said central processor to coordinate comprises means for causing said peripheral processor to perform at least one of said packet processing tasks, and

said central processor is coupled to cause said peripheral processor to perform said at least one of said packet processing tasks.