Processing unit for efficiently determining a packet's destination in a packet-switched network

• US 20060117126A1
• Filed: 01/04/2006
• Published: 06/01/2006
• Est. Priority Date: 07/30/2001
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Mehrotra, Sharad, Li, Anthony J., Lynch, William L., Leung, Arthur Jr.
• Granted Patent: US 7,418,536 B2
• Time in Patent Office: Days
• US Class Current: 710/306
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/54 Organization of routing tables
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags

Abstract

A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of programmable functional units and register files arranged sequentially as stages, for processing packet contexts (which contain the packet'"'"'s destination address) to perform operations, under programmatic control, to determine the destination port of the router for the packet. A single stage of the systolic array may contain a register file and one or more functional units such as adders, shifters, logical units, etc., for performing, in one example, very long instruction word (vliw) operations. The processor may also include a forwarding table memory, on-chip, for storing routing information, and a cross bar selectively connecting the stages of the systolic array with the forwarding table memory.

Claims

1. A processor for use in a router receiving data packets from a network, the router having a plurality of input ports and output ports, the processor comprising:

one or more input buffers for receiving data packets from the input ports of the router; and

a systolic array pipeline for processing the data packets to determine to which output port the data packet should be routed.

2-18. -18. (canceled)