Micro-threaded memory

• US 20060117155A1
• Filed: 11/29/2004
• Published: 06/01/2006
• Est. Priority Date: 11/29/2004
• Status: Active Grant

• Current Assignee: K.Mizra LLC
• Original Assignee: Rambus Inc.
• Inventors: Bellows, Chad A., Richardson, Wayne S., Lai, Lawrence, Hampel, Craig E., Ware, Frederick A.
• Granted Patent: US 8,595,459 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers

Abstract

A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

Claims

1. A memory device comprising:

storage banks each including a plurality of rows of storage cells, wherein a minimum time interval is imposed between successive accesses to a selected one of the rows of storage cells; and

data path circuitry to transfer first data and second data between the storage banks and an external signal path during a first interval that is not longer than the minimum time interval, the first data being indicated by a first memory access request and the second data being indicated by a second memory access request.

2. The memory device of claim 1 wherein the first data and the second data total to an amount of data not greater than a product of the minimum time interval and the signaling bandwidth of the external signal path bandwidth.

3. The memory device of claim 1 wherein the data path circuitry comprises an interface to the external signal path, the interface including at least a predetermined number of contacts that corresponds to a number of constituent signal lines in the external signal path.

4. The memory device of claim 3 wherein the interface is a synchronous interface configured to transmit data via each of the predetermined number of contacts at a first data rate, and wherein the external signal path has a signaling bandwidth that is a function of the first data rate and the number of constituent signal lines in the external signal path.

5. The memory device of claim 4 wherein the first data and the second data constitute an amount of data not greater than the signaling bandwidth of the external signal path multiplied by the minimum access time interval.

6. The memory device of claim 1 wherein the plurality of rows of storage cells comprise dynamic random access memory cells.

7. The memory device of claim 1 wherein the minimum time interval comprises an amount of time required to complete an access directed to the selected row.

8. The memory device of claim 7 wherein the amount of time required to complete an access directed to the selected row includes a tolerance interval to account for access time variation.

9. The memory device of claim 1 wherein the minimum time interval is a t_CC interval.

10. The memory device of claim 1 wherein the minimum time interval is imposed, at least in part, by a time required to free resources used within the memory device to complete a first access of the successive accesses, the resources including at least a portion of the data path circuitry.

11. The memory device of claim 1 wherein the data path circuitry comprises:

a first data interface to transfer the first data between a first portion of the external signal path and a first storage bank of the storage banks; and

a second data interface to transfer the second data between a second portion of the external signal path and a second storage bank of the storage banks.

12. The memory device of claim 1 further comprising a request interface to receive the first and second memory access requests and to initiate transfer of the first data and second data in response.

13. The memory device of claim 1 wherein the first and second memory access requests are memory read requests, and wherein the data path circuitry is configured to transfer the first data and the second data from the storage banks to the external signal path in response to the memory read requests.

14. A method of operation in a memory device, the method comprising:

receiving first and second memory read requests; and

outputting data from the memory device in response to each of the first and second memory read requests during a time interval not longer than a minimum time interval imposed between successive accesses to a selected row of storage cells within the memory device.

15. The method of claim 14 wherein outputting data from the memory device in response to each of the first and second memory read requests comprises outputting the data synchronously with respect to a timing signal.

16. The method of claim 15 wherein the minimum time interval corresponds to a predetermined number of transitions of the timing signal.

17. The method of claim 16 wherein the timing signal is a clock signal.

18. The method of claim 16 wherein the timing signal is a strobe signal.

19. The method of claim 14 wherein outputting data from the memory device in response to each of the first and second memory read requests comprises outputting first data from at least one storage location indicated by the first memory read request and outputting second data from at least one storage location indicated by the second memory read request.

20. A method of operation within a memory device comprising:

subdividing a data transfer envelope of the memory device into multiple partitions; and

allocating the multiple partitions to respective memory access transactions.

21. The method of claim 20 wherein the memory device is a dynamic random access memory (DRAM) device and wherein the data transfer envelope corresponds to a product of the bandwidth of an external signaling path coupled to the DRAM device and a minimum time between successive accesses to a given bank of sense amplifiers within the DRAM device.

22. The method of claim 20 wherein the memory device is a dynamic random access memory (DRAM) device and wherein the data transfer envelope corresponds to a product of a data transfer bandwidth of the DRAM device and a minimum time between successive accesses to a selected bank of sense amplifiers within the DRAM device.

23. The method of claim 20 wherein subdividing a data transfer envelope of the memory device comprises spatially partitioning an interface to a plurality of external signal lines into a first interface to a first subset of the external signal lines and a second interface to a second subset of the external signal lines.

24. The method of claim 23 wherein allocating the multiple partitions to respective memory access transactions comprises:

transferring first data between the first subset of external signal lines and a storage location within the memory device indicated by a first memory access transaction; and

transferring first data between the second subset of external signal lines and a storage location within the memory device indicated by a second memory access transaction.

25. The method of claim 20 wherein subdividing a data transfer envelope of the memory device comprises temporally partitioning the data transfer envelope into distinct first and second time intervals and wherein allocating the multiple partitions to respective memory access transactions comprises (i) transferring first data, during the first time interval, between an external signal path and a storage location within the memory device indicated by a first memory access request and (ii) transferring second data, during the second time interval, between an external signal path and a storage location within the memory device indicated by a second memory access request.

26. A method of operation in a memory device, the method comprising:

receiving first and second memory read requests; and

concurrently outputting first data and second data from the memory device in response to the first and second memory read requests, respectively.

27. The method of claim 26 wherein receiving the first memory read request comprises receiving a first read command and a first address, and wherein outputting data in response to the first memory read request comprises outputting data from at least one storage location indicated by the first address.

28. The method of claim 27 wherein outputting data from at least one storage location indicated by the first address comprises:

transferring data from at least one latching element within a bank of latching sense amplifiers to a transmit circuit; and

transmitting a signal having a signal level determined, at least in part, on the data transferred from the at least one latching element.

29. The method of claim 28 wherein outputting data from at least one storage location indicated by the first address further comprises transferring a row of data, including the first data, from a row of storage cells within the memory device to the bank of latching sense amplifiers

30. The method of claim 28 further comprising:

receiving a row activation request prior to receiving the first memory read request, the row activation request indicating a row of storage cells within the memory device; and

transferring a row of data, including the first data, from the row of storage cells to the bank of latching sense amplifiers in response to the row activation request.

31. The method of claim 27 wherein receiving the second memory read request comprises receiving a second read command and a second address, and wherein outputting data in response to the second memory request comprises outputting data from at least one storage location indicated by the second address.

32. The method of claim 31 wherein the first and second addresses comprise column addresses.

33. The method of claim 31 wherein the first and second addresses each comprise a bank address field and a column address field, and wherein the bank address field of the first address is different from the bank address field of the second address.

34. The method of claim 27 wherein receiving the second memory read request comprises receiving a second address that is associated with the first read command, and wherein outputting data in response to the second memory request comprises outputting data from at least one storage location indicated by the second address.

35. The method of claim 26 wherein receiving first and second memory read requests comprises receiving a multi-address request comprising a read command, a first address and a second address, and wherein outputting data in response to the first and second memory read requests comprises outputting data from at least one storage location indicated by the first address and outputting data from at least one storage location indicated by the second address.

36. The method of claim 35 wherein the first address comprises a first bank address field and a first column address field, and the second address comprises a second bank address field and a second column address field.

37. The method of claim 35 wherein the first and second addresses are column addresses and wherein the multi-address request further comprises a first bank address that specifies a storage bank within the memory device to which the first and second memory read requests are directed.

38. The method of claim 37 wherein at least one of the first and second addresses comprises:

a bank address field that specifies one of a plurality of storage banks within the memory device; and

a column address field that specifies one of a plurality of column locations within a row of data retrieved from the one of the plurality of storage banks.

39. The method of claim 26 wherein receiving first and second memory read requests comprises receiving a read command, a first address and an offset indicator, and wherein outputting data in response to the first read requests comprises outputting data from at least one storage location indicated by the first address, and wherein outputting data in response to the second memory read request comprises (i) determining a second address based, at least in part, on the first address and the offset indicator and (ii) outputting data from at least one storage location indicated by the second address.

40. The method of claim 39 wherein determining a second address based, at least in part, on the first address and the offset indicator comprises combining the offset indicator and the first address to produce the second address.

41. The method of claim 39 wherein determining a second address based, at least in part, on the first address and the offset counter comprises:

selecting one of a plurality of previously stored offset values based on the offset indicator; and

combining the one of the plurality of previously stored offset values with the first address to produce the second address.

42. The method of claim 41 wherein combining the one of the plurality of previously stored offset values with the first address comprises adding the one of the plurality of previously stored offset values to the first address.

43. A memory device comprising:

a first plurality of storage banks; and

a plurality of control circuits coupled respectively to the first plurality of storage banks and configured to enable concurrent access to column-address-specified storage locations within at least two of the storage banks.

44. The memory device of claim 43 wherein the plurality of control circuits comprise:

a first plurality of address decoding circuits coupled respectively to the first plurality of storage circuits to enable access to storage locations therein in response to control information including, at least, a column address; and

a plurality of control storage circuits coupled respectively to the address decoding circuit to provide the control information thereto.

45. The memory device of claim 44 further comprising a request decoder to receive signals indicative of the control information via a request interface and configured to selectively load the control information into the plurality of control storage circuits.

46. The memory device of claim 43 further comprising a second plurality of storage banks and wherein each of the plurality of control circuits is coupled to a respective storage bank of the second plurality of storage banks.

47. The memory device of claim 43 wherein each storage bank of the first plurality of storage banks comprises a storage array and a set of sense amplifiers coupled to the storage array.

48. The memory device of claim 47 wherein the set of sense amplifiers comprise latching sense amplifiers coupled to bit lines of the storage array and configured to store contents of a selected row of memory cells within the storage array.

49. The memory device of claim 48 wherein the column-address-specified storage locations within the at least two of the storage banks comprise a subset of the latching sense amplifiers within a first storage bank of the at least two storage banks and a subset of the latching sense amplifiers within a second storage bank of the at least two storage banks.

50. A method of controlling a memory device, the method comprising:

transmitting to the memory device a first memory access request that specifies a storage location to be accessed within a first storage bank of the memory device; and

a predetermined time after transmitting the first memory access request, transmitting to the memory device a second memory access request that specifies a storage location to be accessed within a second storage bank of the memory device, the predetermined time being substantially less than a minimum time interval imposed between successive accesses to a selected row of storage cells within the memory device.

51. The method of claim 50 wherein the first and second memory access requests are memory read requests.

52. The method of claim 50 wherein the first and second memory access requests are memory write requests.

53. The method of claim 50 further comprising receiving, during a first time interval, first data output from the memory device in response to the first memory access request and second data output from the memory device in response to the second memory access request, the first time interval having substantially the same duration as the minimum time interval imposed between successive accesses to a selected row of storage cells within the memory device.

54. The method of claim 50 wherein receiving the first data and the second data during the first time interval comprises receiving the first data and the second data concurrently during the first time interval.

55. The method of claim 50 wherein receiving the first data and the second data during the first time interval comprises receiving the first data and second data in distinct time intervals within the first time interval.

56. A memory device comprising:

means for receiving first and second memory access requests; and

means for transferring first data and second data between storage arrays of the memory device and an external signal path in response to the first and second memory access requests, respectively.

57. Computer-readable media having information embodied therein that includes a description of a memory device, the information including descriptions of:

storage banks each including a plurality of rows of storage cells, wherein a minimum time interval is imposed between successive accesses to a selected row of the rows of storage cells; and

data path circuitry to transfer first data and second data between the storage banks and an external signal path during a first interval not longer than the minimum time interval, the first data being indicated by a first memory access request and the second data being indicated by a second memory access request.