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LSI physical designing method, program, and apparatus

  • US 20060117288A1
  • Filed: 02/22/2005
  • Published: 06/01/2006
  • Est. Priority Date: 11/29/2004
  • Status: Active Grant
First Claim
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1. An LSI physical designing method comprising:

  • a floor plan processing step wherein a floor plan for arranging a plurality of circuit blocks including a circuit block of a non-rectangular area into a chip is formed;

    a layout step wherein the circuit block of said non-rectangular area is divided into a plurality of rectangular areas and they are arranged in said chip so as to be adapted to said floor plan; and

    a wiring step wherein said plurality of circuit blocks including the circuit block of said non-rectangular area are mutually wired.

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