LSI physical designing method, program, and apparatus

• US 20060117288A1
• Filed: 02/22/2005
• Published: 06/01/2006
• Est. Priority Date: 11/29/2004
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Katagiri, Hideaki
• Granted Patent: US 7,308,667 B2
• Time in Patent Office: Days
• US Class Current: 716/123
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

In addition to a rectangular shape, a non-rectangular shape is enabled to be handled as a physical design unit, thereby miniaturizing a chip and reducing the costs. A floor plan processing unit forms a floor plan for arranging a plurality of circuit blocks including a non-rectangular area into the chip. A layout processing unit divides each of a plurality of non-rectangular circuit blocks having non-rectangular areas into a plurality of rectangular areas and arranges them into the chip so as to be adapted to the floor plan. A wiring processing unit mutually wires the plurality of circuit blocks. The non-rectangular area is constructed by a set of a plurality of division rectangular areas and has a data structure showing a set of two-dimensional coordinate values indicating diagonal vertices of the plurality of division rectangular areas. The non-rectangular areas are also introduced with respect to the cells which are arranged in the circuit block.

Claims

1. An LSI physical designing method comprising:

a floor plan processing step wherein a floor plan for arranging a plurality of circuit blocks including a circuit block of a non-rectangular area into a chip is formed;

a layout step wherein the circuit block of said non-rectangular area is divided into a plurality of rectangular areas and they are arranged in said chip so as to be adapted to said floor plan; and

a wiring step wherein said plurality of circuit blocks including the circuit block of said non-rectangular area are mutually wired.

2. A method according to claim 1, wherein said non-rectangular area is constructed by a set of the plurality of division rectangular areas and has a data structure showing a set of two-dimensional coordinate values indicating diagonal vertices of said plurality of division rectangular areas.

3. A method according to claim 1, wherein in said floor plan processing step, after a plurality of circuit blocks having the rectangular areas are arranged in said chip, a pair of adjacent circuit blocks having empty areas are searched, a self rectangular empty area is deleted from a part of an opposite side of one of said circuit blocks, a self rectangular empty area is deleted from a residual portion of an opposite side of the other circuit block, and a pair of non-rectangular areas having concave/convex fitting shapes are formed.

4. A method according to claim 1, wherein in said floor plan processing step, after the plurality of circuit blocks having the rectangular areas are arranged in said chip, a pair of adjacent circuit blocks having a jammed area and an empty area are searched, a rectangular area is added to a part of an opposite side of the circuit block having the jammed area, a shape corresponding to said added rectangular area is deleted from a portion of an opposite side of the circuit block having the empty area, and a pair of non-rectangular areas having concave and convex fitting shapes are formed.

5. A method according to claim 1, wherein in said layout step, said non-rectangular area is handled as a set of a plurality of division rectangular areas, in the case where at least one of said plurality of division rectangular areas overlaps the division rectangular area of another non-rectangular area, it is determined that said two non-rectangular areas overlap each other, and the overlap is eliminated by re-layout.

6. A method according to claim 1, further comprising a cell layout step wherein cells are arranged in the circuit block having said non-rectangular area,

and wherein in said cell layout step,

when said arranged cells are included in one or a plurality of division rectangular areas, it is determined that they are included in said non-rectangular area, and

when the arranged cells are not included in any one of said plurality of division rectangular areas or a part of said cells are included in said division rectangular area, it is determined that said cells are not included in said non-rectangular area.

7. A method according to claim 1, wherein in said layout step, the cells of the non-rectangular areas are further arranged in said circuit block.

8. A computer-readable storage medium which stores an LSI physical designing program allowing a computer to execute:

a floor plan processing step wherein a floor plan for arranging a plurality of circuit blocks including a circuit block of a non-rectangular area into a chip is formed;

a layout step wherein the circuit block of said non-rectangular area is divided into a plurality of rectangular areas and they are arranged in said chip so as to be adapted to said floor plan; and

a wiring step wherein the plurality of circuit blocks including the circuit block of said non-rectangular area are mutually wired.

10. A storage medium according to claim 8, wherein in said floor plan processing step, after a plurality of circuit blocks of the rectangular areas are arranged in said chip, a pair of adjacent circuit blocks having empty areas are searched, a self rectangular empty area is deleted from a part of an opposite side of one of said circuit blocks, a self rectangular empty area is deleted from a residual portion of an opposite side of the other circuit block, and a pair of non-rectangular areas having concave/convex fitting shapes are formed.

11. A storage medium according to claim 8, wherein in said floor plan processing step, after the plurality of circuit blocks having the rectangular areas are arranged in said chip, a pair of adjacent circuit blocks having a jammed area and an empty area are searched, a rectangular area is added to a part of an opposite side of the circuit block having the jammed area, a shape corresponding to said added rectangular area is deleted from a portion of an opposite side of the circuit block having the empty area, and a pair of non-rectangular areas having concave and convex fitting shapes are formed.

12. A storage medim according to claim 8, wherein in said layout step, said non-rectangular area is handled as a set of a plurality of division rectangular areas, in the case where at least one of said plurality of division rectangular areas overlaps the division rectangular area of another non-rectangular area, it is determined that said two non-rectangular areas overlap each other, and the overlap is eliminated by re-layout.

13. A storage medium according to claim 8, further comprising a cell layout step wherein cells are arranged in the circuit block having said non-rectangular area,

and wherein in said cell layout step,

when said arranged cells are included in one or a plurality of division rectangular areas, it is determined that they are included in said non-rectangular area, and

when the arranged cells are not included in any one of said plurality of division rectangular areas or a part of said cells are included in said division rectangular area, it is determined that said cells are not included in said non-rectangular area.

14. A storage medium according to claim 8, wherein in said layout step, the cells having the non-rectangular areas are further arranged in said circuit block.

9. A storage medium according to claim 9, wherein said non-rectangular area is constructed by a set of the plurality of division rectangular areas and has a data structure showing a set of two-dimensional coordinate values indicating diagonal vertices of said plurality of division rectangular areas.

15. An LSI physical designing apparatus comprising:

a floor plan processing unit which forms a floor plan for arranging a plurality of circuit blocks including a circuit block of a non-rectangular area into a chip;

a layout processing unit which divides the circuit block of the non-rectangular area into a plurality of rectangular areas and arranges said rectangular areas into said chip so as to be adapted to said floor plan; and

a wiring processing unit which mutually wires the plurality of circuit blocks including the circuit block having said non-rectangular area.

16. An apparatus according to claim 15, wherein said non-rectangular area is constructed by a set of the plurality of division rectangular areas and has a data structure showing a set of two-dimensional coordinate values indicating diagonal vertices of said plurality of division rectangular areas.

17. An apparatus according to claim 15, wherein after a plurality of circuit blocks of the rectangular areas are arranged in said chip, said floor plan processing unit searches for a pair of adjacent circuit blocks having empty areas, deletes a self rectangular empty area from a part of an opposite side of one of said circuit blocks, deletes a self rectangular empty area from a residual portion of an opposite side of the other circuit block, and forms a pair of non-rectangular areas having concave/convex fitting shapes.

18. An apparatus according to claim 15, wherein after the plurality of circuit blocks of the rectangular areas are arranged in said chip, said floor plan processing unit searches for a pair of adjacent circuit blocks having a jammed area and an empty area, adds a rectangular area to a part of an opposite side of the circuit block having the jammed area, deletes a shape corresponding to said added rectangular area from a portion of an opposite side of the circuit block having the empty area, and forms a pair of non-rectangular areas having concave and convex fitting shapes.

19. An apparatus according to claim 15, wherein said layout processing unit handles said non-rectangular area as a set of a plurality of division rectangular areas, in the case where at least one of said plurality of division rectangular areas overlaps the division rectangular area of another non-rectangular area, determines that said two non-rectangular areas overlap each other, and eliminates the overlap by re-layout.

20. An apparatus according to claim 15, further comprising a cell layout processing unit which arranges cells into the circuit block having said non-rectangular area,

and wherein said cell layout processing unit

determines that said arranged cells are included in said non-rectangular area when said arranged cells are included in one or a plurality of division rectangular areas, and

determines that said arranged cells are not included in said non-rectangular area when said arranged cells are not included in any one of said plurality of division rectangular areas or a part of said cells are included in said division rectangular area.

21. An apparatus according to claim 15, wherein said layout processing unit further arranges the cells having the non-rectangular areas into said circuit block.