Hardware multithreading systems and methods
First Claim
1. A multithreaded microcontroller comprising:
- a set of special-purpose multithreading registers including a set of thread state registers storing a plurality of thread states for a corresponding plurality of threads; and
thread control logic connected to the set of multithreading registers, comprising;
thread state transition logic connected to the set of thread state registers and configured to control thread suite transitions for the plurality of threads; and
thread instructions execution logic connected to the set of thread state registers and configured to execute a set of multithreading system call machine code instructions.
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Abstract
According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities. A hardware thread profiler including global, run and wait profiler registers is used to monitor thread performance to facilitate software development.
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Citations
94 Claims
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1. A multithreaded microcontroller comprising:
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a set of special-purpose multithreading registers including a set of thread state registers storing a plurality of thread states for a corresponding plurality of threads; and
thread control logic connected to the set of multithreading registers, comprising;
thread state transition logic connected to the set of thread state registers and configured to control thread suite transitions for the plurality of threads; and
thread instructions execution logic connected to the set of thread state registers and configured to execute a set of multithreading system call machine code instructions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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41. A multithreaded data processing method comprising:
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storing a plurality of thread states for a corresponding plurality of threads in a set of thread state registers;
controlling thread state transitions for the plurality of threads using thread state transition logic connected to the set of thread state registers; and
executing a set of multithreading system call machine code instructions using thread instructions execution logic connected to the set of thread state registers. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70)
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71. A multithreaded microcontroller comprising:
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an instruction fetching unit configured to receive a set of machine-code instructions for a plurality of threads, the set of instructions including a set of arithmetic and logical instructions, and a set of multithreading system call instructions;
an arithmetic logic unit connected to the instruction fetching unit and configured to receive and execute the set of arithmetic and logical instructions; and
a hardware thread controller connected to the instruction fetching unit and the arithmetic logic unit, configured to receive and execute the set of multithreading system call instructions. - View Dependent Claims (72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84)
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85. A data processing apparatus comprising:
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a plurality of special-purpose hardware cores integrated on a chip; and
a multithreaded microcontroller integrated on the chip and connected to the plurality of cores, the microcontroller controlling a plurality of threads including a first thread communicating with a first core and a second thread communicating with a second core, the multithreaded microcontroller including a set of special-purpose multithreading registers including a set of thread state registers storing a plurality of thread states for the plurality of threads; and
thread control logic connected to the set of multithreading registers, comprising;
thread state transition logic connected to the set of thread state registers and configured to control thread state transitions for the plurality of threads; and
thread instructions execution logic connected to the thread state transition logic and configured to execute a set of multithreading system call machine code instructions. - View Dependent Claims (86)
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87. A data processing apparatus comprising:
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a multithreaded instruction execution unit configured to run a plurality of threads; and
a hardware thread profiler connected to the multithreaded instruction execution unit, the thread profiler comprising;
thread profiling logic configured to collect thread profiling data for the plurality of threads, the thread profiling data comprising at least one datum selected from a thread state transition count and a time period spent by a thread in a set of thread states; and
a set of thread profiling registers connected to the thread profiling logic and storing the thread profiling data. - View Dependent Claims (88, 89, 90, 91, 92, 93)
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94. A data processing apparatus comprising:
a set of special-purpose multithreading registers including
Specification