Thin film transistor array panel and method for manufacturing the same

• US 20060118793A1
• Filed: 10/27/2005
• Published: 06/08/2006
• Est. Priority Date: 12/08/2004
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yang, Sung-Hoon, Kim, Byoung-June, Girotra, Kunal Satyabhushan
• Application Number:
  US11/262,163
• Publication Number:
  US 20060118793A1
• Time in Patent Office: Days
• US Class Current: 257/79
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT

Abstract

A TFT array panel including a substrate, a gate line having a gate electrode, a gate insulating layer formed on the gate line, a data line having a source electrode and a drain electrode spaced apart from the source electrode, a passivation layer formed on the data line and the drain electrode, and a pixel electrode connected to the drain electrode is provided. The TFT array panel further includes a protection layer including Si under at least one of the gate insulating layer and the passivation layer to enhance reliability.

Claims

1. A TFT array panel comprising:

a substrate;

a gate line including a gate electrode formed over the substrate;

a gate insulating layer formed over the gate line;

a data line including a source electrode and a drain electrode facing and apart from the source electrode formed over the gate insulating layer;

a passivation layer formed over the data line and the drain electrode; and

a pixel electrode electrically connected to the drain electrode

wherein a protection layer including Si is located under at least one of the gate insulating layer and the passivation layer.

2. The TFT array panel of claim 1, wherein the protection layer is formed of SiO2.

3. The TFT array pane claim 1, wherein the protection layer is formed of SiON.

4. The TFT array panel of claim 3, wherein the nitrogen concentration in the protection layer increases as the more upper portion of the protection layer.

5. The TFT array panel of claim 1, wherein the protection layer is formed of silicide.

6. The TFT array panel of claim 1, wherein at least one of the gate line, the data line, and the drain electrode includes Cu or Cu alloy.

7. The TFT array panel of claim 6, wherein at least one of the gate line, the data line, and the drain electrode includes a first conductive layer and a second conductive layer including Cu.

8. The TFT array panel of claim 7, wherein the first conductive layer includes at least one of Mo, Cr, Ti, Ta, alloys thereof and nitrides thereof.

9. The TFT array panel of claim 1, wherein the thickness of the protection layer is about 30 Å

to 300 Å

10. A method of manufacturing a TFT array panel comprising:

forming a gate line including a gate electrode over a substrate;

forming a gate insulating layer over the gate line;

forming a semiconductor layer over the gate insulating layer;

forming a data line including a source electrode and a drain electrode spaced apart from the source electrode over the gate insulating layer and the semiconductor layer;

forming a passivation layer on the data line and the drain electrode; and

forming a pixel electrode connected to the drain electrode,

wherein a protection layer including Si is formed before at least one of forming the gate insulating layer and forming the passivation layer.

11. The method of claim 10, wherein the protection layer is formed of SiO2.

12. The method of claim 10, wherein the protection layer is formed of SiON.

13. The method of claim 10, wherein the protection layer is formed by forming an amorphous silicon layer and annealing the amorphous silicon layer.

14. The method claim 13, wherein the amorphous silicon layer is annealed in about 400°

C. to 800°

C.

15. The method of claim 10, wherein the thickness of the protection layer is about 30 Å

to 300 Å

.

16. The method of claim 10, wherein at least one of the gate line and the data line includes Cu or Cu alloy.

17. The method of claim 10, wherein at least one of the gate line and the data line is formed by forming sequentially a first conductive layer and a second conductive layer including Cu.

18. The method of claim 17, wherein the first conductive layer includes at least one of Mo, Cr, Ti, Ta, alloys thereof, and nitrides thereof.