Fast switching power insulated gate semiconductor device

• US 20060118832A1
• Filed: 01/21/2004
• Published: 06/08/2006
• Est. Priority Date: 01/21/2003
• Status: Abandoned Application

• Current Assignee: Northwest University
• Original Assignee: Northwest University
• Inventors: De Jager, Ocker Cornelis, Visser, Barend
• Application Number:
  US10/542,720
• Publication Number:
  US 20060118832A1
• Time in Patent Office: Days
• US Class Current: 257/232
• CPC Class Codes: H01L 25/07 the devices being of a type provided for in group H01L29/00
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches

Abstract

An insulated gate semiconductor device (30) includes a gate (34), a source terminal (36), a drain terminal (38) and a variable input capacitance at the gate. A ratio between the input capacitance (C_fiss) when the device is on and the input capacitance C_iiss when the device is off is less than two and preferably substantially equal to one. This is achieved in one embodiment of the invention by an insulation layer 32 at the gate having an effective thickness d_ins larger than a minimum thickness.

Claims

1. An insulated gate device comprising a gate connected to a gate terminal and having a variable input capacitance at the gate terminal as the device is switched between an off state and an on state, a ratio between a final value of the capacitance when the device is on and an initial value of the capacitance when the device is off is smaller than 2.0.

2. A device as claimed in claim 1 comprising a power metal oxide silicon field effect transistor (MOSFET).

3. A device as claimed in claim 1 wherein the ratio is less than 1.5.

4. A device as claimed in claim 3 wherein the ratio is substantially equal to 1.

5. A device as claimed in claim 1 comprising a capacitor connected between the gate terminal and the gate of the device.

6. A device as claimed in claim 2 wherein the MOSFET has a vertical structure in that the gate and a source of the device are provided on one face of a chip body of the device and a drain of the MOSFET is provided on an opposite face of the body.

7. A device as claimed in claim 6 wherein the capacitor is integrated on the chip body.

8. A device as claimed in claim 7 wherein the capacitor is superimposed on the gate of the MOSFET.

9. A device as claimed in claim 5 wherein the capacitor is a discrete component connected in series between the gate and the gate terminal and packaged in the same package.

10. A device as claimed in claim 5 wherein the gate is connected directly to a fourth terminal of the device.

11. A device as claimed in claim 9 wherein biasing resistors connected to the gate are included in the same package.