COLLARLESS TRENCH DRAM DEVICE

• US 20060118850A1
• Filed: 12/06/2004
• Published: 06/08/2006
• Est. Priority Date: 12/06/2004
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Parries, Paul C., Ho, Herbert L., Otani, Yoichi, Khan, Babar A.
• Granted Patent: US 7,078,756 B2
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

The present invention provides collarless trench semiconductor memory devices having minimized vertical parasitic FET leakage and methods of forming the same.

Claims

1. A collarless trench semiconductor memory device, comprising:

a semiconductor substrate;

a trench formed in the semiconductor substrate;

a storage capacitor formed within the trench and having a first conductive node, a second conductive node, and a dielectric layer separating the first and second conductive nodes;

a buried strap formed above the storage capacitor and electrically coupled to the first conductive node;

an outdiffusion region adjacent the buried strap and electrically coupled to the buried strap; and

a channel stop region interposed between the outdiffusion region and the second conductive node.

2. The semiconductor memory device of claim 1, wherein the channel stop region is formed by implanting a dopant into the substrate above the second conductive node.

3. The semiconductor memory device of claim 2, wherein the dopant is selected from the group consisting of Boron and BF₂.

4. The semiconductor memory device of claim 2, wherein the dopant is implanted at a tilt angle of approximately seven to ten degrees from perpendicular to the substrate.

5. The semiconductor memory device of claim 1, wherein a thickness of the channel stop region is approximately 1 um to 1.5 um.

6. The semiconductor memory device of claim 1, wherein the substrate comprises a material selected from the group consisting of:

Si, strained Si, Si_1-yC_y, Si_1-x-yGe_xC_y, Si_1-xGe_x, Si alloys, Ge, Ge alloys, GaAs, InAs, InP, III-V semiconductors, and II-VI semiconductors.

7. The semiconductor memory device of claim 1, wherein the first conductive node comprises a material selected from the group consisting of:

doped polysilicon, arsenic-doped polysilicon, doped germanium, metals, suicides, and metallic nitrides.

8. The semiconductor memory device of claim 1, further comprising an insulating layer adjacent the buried strap and adapted to isolate the semiconductor memory device from at least one adjacent device.

9. The semiconductor memory device of claim 1, further comprising a doped well region.

10. The semiconductor memory device of claim 9, wherein the doped well region has a dopant concentration of approximately 1×

10¹⁸ to 1×

10¹⁹ cm<sup>−

3</sup> at a depth of approximately 6000 Å

to 7500 Å

below an upper surface of the substrate.

11. The semiconductor memory device of claim 10, wherein the dopant comprises Boron.

12. The semiconductor memory device of claim 1, further comprising:

a pass-gate device having first and second diffusion regions, wherein the first diffusion region is electrically coupled to the outdiffusion region;

a wordline electrically coupled to the pass-gate device and adapted to activate the pass-gate device; and

a bitline electrically coupled to the second diffusion region of the pass-gate device.

13. The semiconductor memory device of claim 12, further comprising a second pass-gate device electrically isolated from the semiconductor memory device by the insulating layer and adapted to activate an adjacent memory device.

14. A collarless trench semiconductor memory device, comprising:

a semi conductor substrate;

a trench formed in the semiconductor substrate;

a storage capacitor formed within the trench and having a first conductive node, a second conductive node, and a dielectric layer separating the first and second conductive nodes;

a buried strap formed above the storage capacitor and electrically coupled to the first conductive node;

an outdiffusion region adjacent the buried strap and electrically coupled to the buried strap; and

a doped well region formed within the substrate, wherein the doped well region has a dopant concentration of approximately 1×

10¹⁸ to 1×

10¹⁹ cm<sup>−

3</sup> at a depth of approximately 6000 Å

to 7500 Å

below an upper surface of the substrate.

15. The semiconductor memory device of claim 14, wherein the dopant comprises B.

16. The semiconductor memory device of claim 14, wherein the substrate comprises a material selected from the group consisting of:

Si, strained Si, Si_1-yC_y, Si_1-x-yGe_xC_y, Si_1-xGe_x, Si alloys, Ge, Ge alloys, GaAs, InAs, InP, III-V semiconductors, and II-VI semiconductors.

17. The semiconductor memory device of claim 14, wherein the first conductive node comprises a material selected from the group consisting of:

doped polysilicon, As-doped polysilicon, doped germanium, metals, silicides, and metallic nitrides.

18. The semiconductor memory device of claim 14, further comprising an insulating layer adjacent the buried strap and adapted to isolate the semiconductor memory device from at least one adjacent device.

19. The memory device of claim 14, further comprising:

a pass-gate device having first and second diffusion regions, wherein the first diffusion region is electrically coupled to the outdiffusion region;

a wordline electrically coupled to the pass-gate device and adapted to activate the pass-gate device; and

a bitline electrically coupled to the second diffusion region of the pass-gate device.

20. The memory device of claim 19, further comprising a second pass-gate device electrically isolated from the semiconductor memory device by the insulating layer and adapted to activate an adjacent memory device.

21. A method of forming a semiconductor memory device, comprising:

providing a substrate;

forming a trench in the substrate, the trench having a plurality of sidewalls and a bottom;

forming a first conductive node of a storage capacitor within the substrate;

forming a node dielectric of the storage capacitor adjacent at least one of the trench sidewalls;

forming a channel stop region within the substrate above the first conductive node;

forming a second conductive node of the storage capacitor within the trench;

forming a buried strap above the storage capacitor;

forming an outdiffusion region adjacent the buried strap;

forming an active pass-gate device coupled to the outdiffusion region;

forming a wordline coupled to the active pass-gate device; and

forming a bitline coupled to the active pass-gate device.

22. The method of claim 21, wherein the channel stop region is formed before the storage capacitor node dielectric is formed.

23. The method of claim 21, wherein the channel stop region is formed by implanting a dopant into a portion of the substrate above the second conductive node.

24. The method of claim 23, wherein the dopant is implanted at a tilt angle of approximately seven to ten degrees from perpendicular to the substrate.

25. The method of claim 21, further comprising forming an insulating layer adjacent the buried strap, wherein the insulating layer is adapted to isolate the semiconductor memory device from at least one adjacent device.

26. The method of claim 21, further comprising forming a doped well region within the substrate.

27. The method of claim 26, wherein the doped well region is formed by implanting a dopant having a dose of approximately 2¹³ to 1.75¹⁴ cm⁻

2 into the substrate at an implant energy of approximately 200 KeV to 260 KeV.

28. A method of forming a semiconductor memory device, comprising:

providing a substrate,

forming a trench in the substrate having a plurality of sidewalls and a bottom;

forming a first conductive node of a storage capacitor within the substrate;

forming a node dielectric of the storage capacitor adjacent at least one of the trench sidewalls;

forming a second conductive node of the storage capacitor within the trench;

forming a buried strap above the storage capacitor;

forming an outdiffusion region adjacent the buried strap;

forming a doped well region within the substrate, wherein the doped well region is formed by implanting a dopant having a dose of approximately 2¹³ to 1.75 ¹⁴ cm<sup>−

2</sup> into the substrate at an implant energy of approximately 200 KeV to 260 KeV;

forming an active pass-gate device coupled to the outdiffusion region;

forming a wordline coupled to the active pass-gate device; and

forming a bitline coupled to the active pass-gate device.

29. The method of claim 28, further comprising forming an insulating layer adjacent the buried strap adapted to isolate the semi conductor memory device from at least one adjacent device.