Nonvolatile semiconductor memory device having excellent charge retention and manufacturing process of the same

• US 20060118853A1
• Filed: 12/06/2004
• Published: 06/08/2006
• Est. Priority Date: 12/06/2004
• Status: Active Grant

• Current Assignee: Asahi Glass Company, Limited (AGC, Inc.), Tohoku University National Universities Corporation
• Original Assignee: Asahi Glass Company, Limited (AGC, Inc.), Tohoku University National Universities Corporation
• Inventors: Koyanagi, Mitsumasa, Takata, Masaaki
• Granted Patent: US 7,355,238 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: Y10S 977/943 Information storage or retrieval using nanostructure

Abstract

There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult to be achieved due to the essential problem. In order to solve the above problem, in the nonvolatile semiconductor memory device of the present invention, a material having large work function or large electron affinity or a material having a work function close to that of semiconductor substrate or of a control gate, is employed for a floating gate retaining charges. Further, an amorphous material having small electron affinity for an insulating matrix is used. Further, at a time of deposition of charge retention layer, the supply ratio of the nano-particle material and the insulating matrix material, such as the mixture ratio of materials of both phases in a target in a sputtering method, is adjusted. By these methods, the charge retention characteristic of the floating-gate type nonvolatile semiconductor memory device can be improved, and the above-mentioned problem of the nonvolatile semiconductor memory device can be solved.

Claims

1. A nonvolatile semiconductor memory device comprising a source region and a drain region formed on a surface of a semiconductor substrate;

a channel-forming region formed so as to connect the source region and the drain region or so as to be sandwiched between the source region and the drain region;

a tunnel insulating film formed in contact with the channel-forming region;

a charge retention layer formed adjacently to the tunnel insulating film;

a gate insulating film formed adjacently to the charge retention layer; and

a control gate formed adjacently to the gate insulating film, characterized in that the charge retention layer consists of an insulating matrix containing, per nonvolatile semiconductor memory device, one conductive nano-particle which is made of at least one single-element substance or chemical compound that functions as a floating gate and has a particle size of at most 5 nm, or containing a plurality of conductive nano-particles of the same type independently dispersed with a density of from 10⁺¹² to 10⁺¹⁴ particles per square centimeter in the charge retention layer;

the insulating matrix is amorphous and has an electron affinity of at most 1.0 eV; and

the work function of the conductive nano-particles is at least 4.2 eV.

2. The nonvolatile semiconductor memory device according to claim 1, wherein the difference between the work function of the nano-particles and the work function of the semiconductor substrate is at most 0.5 eV.

3. The nonvolatile semiconductor memory device according to claim 1, wherein the difference between the work function of the nano-particles and the work function of the control gate is at most 0.5 eV.

4. The nonvolatile semiconductor memory device according to claim 1, wherein the distance between surfaces of the nano-particles adjacent to each other is from 1 to 5 nm.

5. The nonvolatile semiconductor memory device according to claim 1, wherein the insulating matrix constituting the charge retention layer is made of at least one chemical compound selected from the group consisting of an oxide, a carbide, a nitride, a boride, a silicide, and a fluoride.

6. The nonvolatile semiconductor memory device according to claim 1, wherein the nano-particles constituting the charge retention layer are dispersed two-dimensionally or three-dimensionally in the insulating matrix.

7. A process for manufacturing the nonvolatile semiconductor memory device that has the charge retention layer wherein the nano-particles are dispersed two-dimensionally or three-dimensionally in the insulating matrix as defined in claim 6, characterized by forming the charge retention layer in a self-organizing manner by physical vapor deposition of each material to constitute the nano-particles and the insulating matrix.

8. The process for manufacturing the nonvolatile semiconductor memory device according to claim 7, wherein the physical vapor deposition is performed by a sputtering method.

9. A nonvolatile semiconductor memory device comprising a source region and a drain region formed on a surface of a semiconductor substrate;

a channel-forming region formed so as to connect the source region and the drain region or so as to be sandwiched between the source region and the drain region;

a tunnel insulating film formed in contact with the channel-forming region;

an charge retention layer formed adjacently to the tunnel insulating film;

a gate insulating film formed adjacently to the charge retention layer; and

a control gate formed adjacently to the gate insulating film, characterized in that the charge retention layer consists of an insulating matrix containing, per nonvolatile semiconductor memory device, one semiconductive or insulating nano-particle which is made of at least one single-element substance or chemical compound that functions as a floating gate and has a particle size of at most 5 nm, or containing a plurality of semiconductive or insulating nano-particles of the same type independently dispersed with a density of from 10⁺¹² to 10⁺¹⁴ particles per square centimeter in the charge retention layer;

the insulating matrix is amorphous and has an electron affinity of at most 1.0 eV; and

the electron affinity of the nano-particles is at least 4.2 eV.

10. The nonvolatile semiconductor memory device according to claim 9, wherein the difference between the work function of the nano-particles and the work function of the semiconductor substrate is at most 0.5 eV.

11. The nonvolatile semiconductor memory device according to claim 9, wherein the difference between the work function of the nano-particles and the work function of the control gate is at most 0.5 eV.

12. The nonvolatile semiconductor memory device according to claim 9, wherein the distance between surfaces of the nano-particles adjacent to each other is from 1 to 5 nm.

13. The nonvolatile semiconductor memory device according to claim 9, wherein the insulating matrix constituting the charge retention layer is made of at least one chemical compound selected from the group consisting of an oxide, a carbide, a nitride, a boride, a silicide, and a fluoride.

14. The nonvolatile semiconductor memory device according to claim 9, wherein the nano-particles constituting the charge retention layer are dispersed two-dimensionally or three-dimensionally in the insulating matrix.

15. A process for manufacturing the nonvolatile semiconductor memory device that has the charge retention layer wherein the nano-particles are dispersed two-dimensionally or three-dimensionally in the insulating matrix as defined in claim 14, characterized by forming the charge retention layer in a self-organizing manner by physical vapor deposition of each material to constitute the nano-particles and the insulating matrix.

16. The process for manufacturing the nonvolatile semiconductor memory device according to claim 15, wherein the physical vapor deposition is performed by a sputtering method.