High-frequency switching transistor and high-frequency circuit

• US 20060118884A1
• Filed: 11/04/2005
• Published: 06/08/2006
• Est. Priority Date: 11/05/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Taddiken, Hans, Losehand, Reinhard, Gerlach, Udo
• Granted Patent: US 7,564,103 B2
• Time in Patent Office: Days
• US Class Current: 257/376
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

A high-frequency switching transistor comprises a substrate having a substrate dopant concentration and a barrier region bordering on the substrate, which has a first conductivity type, wherein a barrier region dopant concentration is higher than the substrate dopant concentration. Further, the high-frequency switching transistor comprises a source region embedded in the barrier region, which comprises a second conductivity type different to the first conductivity type, and has a source region dopant concentration, which is higher than the barrier region dopant concentration. Additionally, the high-frequency switching transistor comprises a drain region embedded in the barrier region and disposed offset from the source region, which comprises the second conductivity type and has a drain region dopant concentration, which is higher than the barrier region dopant concentration. Further, the high-frequency switching transistor has a channel region, extending between the source region, wherein the channel region comprises a subregion of the barrier region. Further, the high-frequency switching transistor has an insulation region, which covers the channel region and which is disposed between the channel region and the gate electrode. Such a high-frequency switching transistor allows switching of high-frequency signals with higher high-frequency signal amplitudes as are switchable by conventional high-frequency switching transistors.

Claims

1. A switching transistor, comprising:

a substrate having a substrate dopant concentration;

a barrier region bordering on the substrate, comprising a first conductivity type and having a barrier region dopant concentration, which is higher than the substrate dopant concentration;

a source region embedded in the barrier region, comprising a second conductivity type different to the first conductivity type, and having a source region dopant concentration, which is higher than the barrier region dopant concentration;

a drain region embedded in the barrier region and disposed offset from the source region, comprising the second conductivity type and having a dopant concentration, which is higher than the barrier region dopant concentration;

a channel region extending between the source region and the drain region, wherein the channel region comprises a subregion of the barrier region; and

an insulation region, which covers the channel region and is disposed between the channel region and a gate electrode.

2. The switching transistor according to claim 1, further comprising:

a further barrier region having the second conductivity type, the further barrier region having a dopant concentration that is higher than the substrate dopant concentration; and

a substrate terminal region embedded in the further barrier region, having the first conductivity type and a substrate terminal region dopant concentration, which is higher than the dopant concentration of the further barrier region.

3. The switching transistor according to claim 1, wherein the first conductivity type comprises a p doped semiconductor material and the second conductivity type comprises an n doped semiconductor material.

4. The switching transistor according to claim 1, wherein the first conductivity type comprises an n doped semiconductor material and the second conductivity type a p doped semiconductor material.

5. The switching transistor according to claim 1, wherein the substrate dopant concentration is lower than 10¹⁴ dopant atoms per cubic centimeter.

6. The switching transistor according to claim 1, wherein the drain region dopant concentration, the source region dopant concentration or the substrate terminal region dopant concentration is higher than 10¹⁸ dopant atoms per cubic centimeter.

7. The switching transistor according to claim 1, wherein the barrier region dopant concentration lies between 10¹⁴ and 10¹⁸ dopant atoms per cubic centimeters.

8. The switching transistor according to claim 1, wherein a thickness of the barrier region between the drain region and the substrate or a thickness of the barrier region between the source region and the substrate lies in a range of values between 0.05 μ

m and 1 μ

m.

9. The switching transistor according to claim 2, wherein a thickness of the further barrier region between the substrate and the substrate terminal region lies in a range of values between 0.05 and 1 μ

m.

10. The switching transistor according to claim 1, wherein the channel region comprises a plurality of subchannel regions, which are disposed in series between the source region and the drain region, and wherein the insulation region comprises a plurality of subregions, and the gate electrode comprises a plurality of subgate electrodes, wherein one subinsulation region covers one subchannel region, and every subinsulation region is disposed between the corresponding subchannel region and a subgate electrode.

11. The switching transistor according to claim 2, wherein a spacing between the drain region and the substrate terminal region is at least 1 μ

m.

12. The switching transistor according to claim 10, wherein the subchannel region has a minimum length of 0.1 μ

m.

13. The switching transistor according to claim 12, wherein the channel region has a width within a range of values between 100 μ

m to 500 μ

m.

14. A circuit, comprising:

a switch with a high-frequency switching transistor, comprising,

a substrate having a substrate dopant concentration,

a barrier region bordering on the substrate, comprising a first conductivity type and having a barrier region dopant concentration, which is higher than the substrate dopant concentration,

a source region embedded in the barrier region, comprising a second conductivity type different to the first conductivity type, and having a source region dopant concentration, which is higher than the barrier region dopant concentration,

a drain region embedded in the barrier region and disposed offset from the source region, comprising the second conductivity type and having a dopant concentration, which is higher than the barrier region dopant concentration,

a channel region extending between the source region and the drain region, wherein the channel region comprises a subregion of the barrier region, and

an insulation region, which covers the channel region and is disposed between the channel region and a gate electrode; and

a control circuit configured to open and close the switch depending on a control signal, and operably coupled to provide the gate electrode with a potential for opening the switch, the control circuit further operable to enable a current flow between the source region and the drain region.

15. The circuit according to claim 14, wherein the control circuit is formed to apply an offset voltage between the source region and the drain region relative to the substrate when opening the switch.

16. The circuit according to claim 14, wherein the high-frequency switching transistor further includes a substrate terminal region embedded in a further barrier region, and wherein the control circuit is further configured to provide the substrate terminal region with a potential by using a resistor connected in series to the substrate terminal region.

20. The circuit according to claim 14, wherein the source region of a high-frequency switching transistor is connected to a potential terminal via a first resistor, and the drain region of the high-frequency switching transistor is connected to the potential terminal via a second resistor.

21. The circuit according to claim 14, wherein the potential terminal is connected to a ground terminal of the circuit.

23. The circuit according to claim 14, wherein a second high-frequency switching transistor is connected in series to the first high-frequency switching transistor between the first high-frequency signal terminal and the second high-frequency signal terminal.

24. The circuit according to claim 14, wherein first and second high-frequency terminals are connected in a first branch via a high-frequency switching transistor or a series circuit of high-frequency switching transistors are connected, and wherein the first high-frequency terminal is connected to a potential terminal for a constant potential via a second branch, which comprises a further high-frequency switching transistor or a series circuit of several further high-frequency switching transistors, wherein the circuit is further formed to switch through the further high-frequency switching transistor of the series circuit of further high-frequency switching transistors, when the high-frequency transistor or the series circuit, between the first and second high-frequency terminals is not switched through or to block the further high-frequency switching transistor or the series circuit of further high-frequency transistors when the high-frequency transistor or the series circuit is switched through between the first and second high-frequency terminals.

25. The circuit according to claim 24, wherein the constant potential of the potential terminal is a ground potential of the circuit.

17. A circuit with a high-frequency switching transistor, comprising:

a substrate having a substrate dopant concentration;

a barrier region bordering on the substrate, comprising a first conductivity type and having a barrier region dopant concentration, which is higher than the substrate dopant concentration;

a source region embedded in the barrier region, comprising a second conductivity type different to the first conductivity type, and having a source region dopant concentration, which is higher than the barrier region dopant concentration;

a drain region embedded in the barrier region and disposed offset from the source region, comprising the second conductivity type and having a dopant concentration, which is higher than the barrier region dopant concentration;

a channel region extending between the source region and the drain region, wherein the channel region comprises a subregion of the barrier region; and

an insulation region, which covers the channel region and is disposed between the channel region and a gate electrode,

wherein the circuit is formed to provide the substrate of the high-frequency transistor with an offset voltage in relation to the source region and the drain region.

18. The circuit according to claim 17, further having a partial circuit, which is formed to generate the offset voltage.

19. The circuit according to claim 17, wherein a gate is connected to a node via a resistor, which is connected to a second circuit formed to provide a gate electrode with a voltage for opening or closing the high-frequency switching transistor.

22. The circuit according to claim 17, wherein the high-frequency switching transistor is disposed in a first branch of The circuit between a first high-frequency signal terminal and a second high-frequency signal terminal.

26. The circuit according to claim 22, further comprising at least one further high-frequency switching transistor or a series circuit of high-frequency switching transistors, which are disposed in a third branch wherein the second high-frequency terminal is connected to a third high-frequency terminal through the third branch.

27. The circuit according to claim 26, further having a fourth branch of the circuit, which connects the third high-frequency terminal to a further potential terminal for a constant potential, wherein the fourth branch comprises a high-frequency switching transistor or a series circuit.

28. The circuit according to claim 27, which further comprising a control circuit, which is formed to open one high-frequency switching transistor each of the first and fourth branch in a first switching state, while one high-frequency switching transistor each of the second and third branch is closed, or to open one high-frequency switching transistor each of the second and third branch in a second switching state, while one high-frequency switching transistor each of the first and fourth branch is closed.

29. The circuit according to claim 27, wherein at least one high-frequency switching transistor is disposed between a contact point of the fourth branch with the third branch and the third high-frequency terminal.

30. A circuit with a first terminal, a second terminal, a third terminal and a fourth terminal, comprising:

a first switch, which is formed to switch a first signal from the first terminal to the second terminal or from the first terminal to the fourth terminal; and

a second switch, which is formed to switch a second signal from the third terminal to the second terminal or from the third terminal to the fourth terminal,

wherein the first switch comprises a first switching element with a first high-frequency switching transistor, which is connected between the first terminal and the second terminal, and a second switching element with a second high-frequency switching transistor, which is connected between the first terminal and the fourth terminal, and

wherein the second switch comprises a third switching element with a third high-frequency transistor, which is connected between the third terminal and the second terminal and comprises a fourth switching element with a fourth high-frequency switching transistor, which is connected between the third terminal and the fourth terminal,

wherein the first, second, third and fourth high-frequency switching transistor are controllable such that the fourth high-frequency switching transistor is opened when the first high-frequency switching transistor is opened, the fourth high-frequency switching transistor is closed when the first high-frequency switching transistor is closed, the third high-frequency switching transistor is opened when the second high-frequency switching transistor is opened, and the third high-frequency switching transistor is closed when the high-frequency switching transistor is closed;

wherein the first, second, third and fourth high-frequency switching transistor comprise;

a substrate having a substrate dopant concentration;

a barrier region bordering on the substrate, comprising a first conductivity type and having a barrier region dopant concentration, which is higher than the substrate dopant concentration;

a source region embedded in the barrier region, comprising a second conductivity type different to the first conductivity type, and having a source region dopant concentration, which is higher than the barrier region dopant concentration;

a drain region embedded in the barrier region and disposed offset from the source region, comprising the second conductivity type and having a dopant concentration, which is higher than the barrier region dopant concentration;

a channel region disposed between the source region and the drain region, wherein the channel region comprises a subregion of the barrier region; and

an insulation region, which covers the channel region and is disposed between the channel region and a gate electrode.

31. The circuit according to claim 30, wherein the first, second, third and fourth switching element comprise one series circuit each of several high-frequency switching transistors, comprising:

a substrate having a substrate dopant concentration;

a barrier region bordering on the substrate, comprising a first conductivity type and having a barrier region dopant concentration, which is higher than the substrate dopant concentration;

a source region embedded in the barrier region, comprising a second conductivity type different to the first conductivity type, and having a source region dopant concentration, which is higher than the barrier region dopant concentration;

a drain region embedded in the barrier region and disposed offset from the source region, comprising the second conductivity type and having a dopant concentration, which is higher than the barrier region dopant concentration;

a channel region disposed between the source region and the drain region, wherein the channel region comprises a subregion of the barrier region; and

an insulation region, which covers the channel region and is disposed between the channel region and a gate electrode.

32. The circuit according to claim 30, wherein the first terminal is connectable to a ground potential via a fifth switching element, and wherein the third terminal is connectable to a ground potential via a sixth switching element, wherein the fifth and the sixth switching element each comprise one high-frequency switching transistor, comprising:

a substrate having a substrate dopant concentration;

a barrier region bordering on the substrate, comprising a first conductivity type and having a barrier region dopant concentration, which is higher than the substrate dopant concentration;

a source region embedded in the barrier region, comprising a second conductivity type different to the first conductivity type, and having a source region dopant concentration, which is higher than the barrier region dopant concentration;

a drain region embedded in the barrier region and disposed offset from the source region, comprising the second conductivity type and having a dopant concentration, which is higher than the barrier region dopant concentration;

a channel region extending between the source region and the drain region, wherein the channel region comprises a subregion of the barrier region; and

an insulation region, which covers the channel region and is disposed between the channel region and a gate electrode,

and wherein the circuit is formed to control the fifth and sixth switching element such that when the high-frequency switching transistor of the fifth switching element is closed, the high-frequency switching transistor of the sixth switching element is opened, and that when the high-frequency switching transistor of the fifth switching element is opened, the high-frequency switching transistor of the sixth switching element is closed.