Reduced capacitance resistors

• US 20060118908A1
• Filed: 12/06/2004
• Published: 06/08/2006
• Est. Priority Date: 12/06/2004
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Shaw, Jonathan, Nunn, Kevin R., Erickson, Sean C.
• Granted Patent: US 7,242,074 B2
• Time in Patent Office: Days
• US Class Current: 257/536
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H01L 28/20 Resistors

Abstract

A method for reducing the parasitic capacitance in resistors, and a resistor design embodying this method are described. By creating a p-type or an n-type implant inside of an n-well or a p-substrate, respectively, where the n-well or p-substrate is located in a p-substrate or n-substrate, respectively, a capacitively coupled capacitor is formed in series connection with the parasitic inter-layer dielectric capacitance generated when the resistor is fabricated in the dielectric material. The depletion region formed thereby behaves as a series capacitor which reduces the overall capacitance of the assemblage. The n-well or p-substrate can be placed in electrical connection with a ground potential or brought to a chosen voltage to further increase the depletion region and reduce the capacitance of the resistor.

Claims

1. A resistor having reduced parasitic capacitance comprising:

(a) a chosen dielectric material;

(b) a first substrate disposed in said dielectric material and having a surface thereof implanted to a chosen thickness with an effective amount of at least one first dopant, forming thereby a resistive layer having a chosen area and having an inter-layer dielectric parasitic capacitance; and

(c) a capacitive region disposed in said dielectric material, said capacitive region being series coupled to the inter-layer dielectric parasitic capacitance of said resistive layer.

2. The resistor of claim 1, wherein said series-coupled capacitive region comprises a p-type layer formed on the surface of an n-type substrate, said n-type substrate being disposed within a p-type substrate, wherein the p-type layer comprises an effective amount of at least one second dopant, wherein the p-type layer is approximately co-extensive with said resistive layer and parallel thereto, and wherein the p-type layer is in contact with said dielectric material, thereby generating a depletion region which behaves as a reversed-biased diode having a capacitance which is series-coupled with the inter-layer dielectric capacitance of said resistive layer.

3. The resistor of claim 2, wherein said n-type substrate is placed in electrical connection with a ground potential or a chosen voltage, such that the extent of depletion of the depletion region is increased.

4. The resistor of claim 2, wherein said n-type substrate and said p-type substrate comprise crystalline silicon.

5. The resistor of claim 4, wherein said at least one second dopant comprises boron.

6. The resistor of claim 1, wherein said series-coupled capacitive region comprises a n-type layer formed on the surface of an n-type substrate, said p-type substrate being disposed within an n-type substrate, wherein the n-type layer comprises an effective amount of at least one second selected dopant, wherein the n-type layer is approximately co-extensive with said resistive layer and parallel thereto, and wherein the n-type layer is in contact with said dielectric material, thereby generating a depletion region which behaves as a reversed-biased diode having a capacitance which is series-coupled with the inter-layer dielectric capacitance of said resistive layer.

7. The resistor of claim 6, wherein said p-type substrate is in electrical contact with a ground potential or a chosen voltage, such that the extent of depletion of the depletion region is increased.

8. The resistor of claim 6, wherein said n-type substrate and said p-type substrate comprise crystalline silicon.

9. The resistor of claim 8, wherein said at least one second dopant is selected from the group consisting of arsenic and phosphorus.

10. The resistor of claim 1, wherein said first substrate comprises polysilicon.

11. The resistor of claim 1, wherein said at least one first dopant is selected from the group consisting of boron, phosphorus and arsenic.

12. The resistor of claim 1, wherein said dielectric material comprises a low-k dielectric material.

14. The resistor of claim 1, further comprising at least 2 electrical connections on the resistive layer of said first substrate.

13. The resistor of claim 13, wherein said low-k dielectric material comprises silicon dioxide.

15. A method for reducing the parasitic capacitance of a resistor comprising the steps of:

(a) implanting the surface of a first substrate disposed in a chosen dielectric material with an effective amount of at least one first dopant to a chosen depth, forming thereby a resistive layer having a chosen area and having an inter-layer dielectric parasitic capacitance; and

(b) forming a p-type layer on the surface of an n-type substrate, the n-type substrate being disposed within a p-type substrate and spaced apart from the first substrate, wherein the p-type layer has an effective amount of at least one second dopant, wherein the p-type layer is approximately co-extensive with the resistive layer and parallel thereto, and wherein the p-type layer is in contact with the dielectric material, thereby generating a depletion region which behaves as a reversed-biased diode having a capacitance which is series-coupled with the inter-layer dielectric capacitance of the resistive layer.

16. The method of claim 15, further comprising the step of placing the n-type substrate in electrical connection with an electrical ground potential or a chosen voltage, thereby increasing the depletion region.

17. The method of claim 15, wherein the n-type substrate and said p-type substrate comprise crystalline silicon.

18. The method of claim 15, wherein the at least one second dopant comprises boron.

19. The method of claim 15, wherein the dielectric material comprises a low-k dielectric material.

21. The method of claim 15, further comprising the step of forming electrical connections on the resistive layer.

22. The method of claim 15, wherein the first substrate comprises polysilicon.

23. The method of claim 22, wherein the at least one first dopant is selected from the group consisting of boron, phosphorus and arsenic.

20. The method of claim 20, wherein the low-k dielectric material comprises silicon dioxide.

24. A method for reducing the parasitic capacitance of a resistor comprising the steps of:

(a) implanting the surface of a first substrate disposed in a chosen dielectric material with an effective amount of at least one first dopant to a chosen depth, forming thereby a resistive layer having a chosen area and having an inter-layer dielectric parasitic capacitance; and

(b) forming a n-type layer on the surface of a p-type substrate, the p-type substrate being disposed within the dielectric material and spaced apart from the first substrate, wherein the n-type layer has an effective amount of at least one second dopant, wherein the n-type layer is approximately co-extensive with the resistive layer and parallel thereto, and wherein the n-type layer is in contact with the dielectric material, thereby generating a depletion region which behaves as a reversed-biased diode having a capacitance which is series-coupled with the inter-layer dielectric capacitance of the resistive layer.

25. The method of claim 24, further comprising the step of placing the n-type substrate in electrical connection with an electrical ground potential or a chosen voltage, thereby increasing the depletion region.

26. The method of claim 24, wherein the n-type substrate and said p-type substrate comprise crystalline silicon.

27. The method of claim 26, wherein the at least one second dopant is selected from the group consisting of arsenic and phosphorus.

28. The method of claim 24, wherein the first substrate comprises polysilicon.

29. The method of claim 24, wherein the at least one first dopant is selected from the group consisting of boron, phosphorus and arsenic.

30. The method of claim 24, wherein the dielectric material comprises a low-k dielectric material.

31. The method of claim 30, wherein the low-k dielectric material comprises silicon dioxide.

32. The method of claim 24, further comprising the step of forming electrical connections on the resistive layer.