Alloyed underlayer for microelectronic interconnects

• US 20060118968A1
• Filed: 12/07/2004
• Published: 06/08/2006
• Est. Priority Date: 12/07/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Dominguez, Juan E., Johnston, Steven W.
• Granted Patent: US 7,435,679 B2
• Time in Patent Office: Days
• US Class Current: 257/775
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76858 by diffusing alloying elements
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during thermal post-treatment, such as thermal annealing, conducted after two separately depositing the noble metal and the barrier material, which are substantially soluble in one another. The use of a barrier material within the underlayer prevents the electromigration of the interconnect conductive material and the use of noble material within the underlayer allows for the direct plating of the interconnect conductive material.

Claims

1. A microelectronic interconnect underlayer, comprising an alloyed material including a barrier material and a noble metal.

2. The underlayer of claim 1, wherein said barrier material is a refractory metal.

3. The underlayer of claim 1, wherein said barrier material is selected form the group consisting of tantalum, titanium, tungsten, molybdenum, or zirconium.

4. The underlayer of claim 1, wherein said barrier material is carbided.

5. The underlayer of claim 1, wherein said barrier material is nitrided.

6. The underlayer of claim 1, wherein said noble metal is selected from the group consisting of ruthenium, platinum, palladium, rhenium, osmium, iridium, gold, and rhodium.

7. A method of fabricating an interconnect, comprising:

providing at least one dielectric layer;

forming at least one opening extending into said at least one dielectric layer, wherein said opening is defined by at least one side;

co-depositing a barrier material and a noble metal to form an underlayer to contact said at least one opening side; and

plating at least one conductive material to fill said opening and abut said underlayer.

8. The method of claim 7, wherein co-depositing said barrier material and said noble metal comprises co-depositing a refractory metal barrier material and a noble metal.

9. The method of claim 7, wherein co-depositing said barrier material and said noble metal comprises co-depositing said noble metal and said barrier material selected form the group consisting of tantalum, titanium, tungsten, molybdenum, or zirconium

10. The method of claim 7, wherein co-depositing said barrier material and said noble metal comprises co-depositing a carbided barrier material and said noble metal.

11. The method of claim 7, wherein co-depositing said barrier material and said noble metal comprises co-depositing a nitrided barrier material and said noble metal.

12. The method of claim 7, wherein co-depositing said barrier material and said noble metal comprises co-depositing said barrier material and said noble metal selected from the group consisting of ruthenium, platinum, palladium, rhenium, osmium, iridium, gold, and rhodium.

13. A method of fabricating an interconnect, comprising:

providing at least one dielectric layer;

forming at least one opening extending into said at least one dielectric layer, wherein said opening is defined by at least one side;

sequentially depositing a barrier material and a noble metal at least within said opening;

annealing said barrier material and said noble metal to form an alloyed underlayer; and

plating at least one conductive material to fill said opening and abut said underlayer.

14. The method of claim 13, wherein depositing said barrier material comprises depositing a refractory metal barrier material.

15. The method of claim 13, wherein depositing said barrier material comprises depositing a barrier material selected form the group consisting of tantalum, titanium, tungsten, molybdenum, or zirconium

16. The method of claim 13, wherein depositing said barrier material comprises depositing a carbided barrier material.

17. The method of claim 13, wherein depositing said barrier material comprises depositing a nitrided barrier material.

18. The method of claim 13, wherein depositing said noble metal comprises depositing a noble metal selected from the group consisting of ruthenium, platinum, palladium, rhenium, osmium, iridium, gold, and rhodium.

19. An electronic system, comprising:

an external substrate within a housing; and

at least one microelectronic device package attached to said external substrate, having at least one interconnect having an underlayer comprising an alloyed material including a barrier material and a noble metal; and

an input device interfaced with said external substrate; and

a display device interfaced with said external substrate.

20. The electronic system of claim 19, wherein said barrier material is selected form the group consisting of tantalum, titanium, tungsten, molybdenum, or zirconium.

21. The system of claim 19, wherein said noble metal is selected from the group consisting of ruthenium rhenium, osmium, iridium, gold, and rhodium.