Semiconductor device, its manufacturing method, and radio communication device

• US 20060118970A1
• Filed: 01/06/2006
• Published: 06/08/2006
• Est. Priority Date: 09/05/2001
• Status: Active Grant

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Renesas Eastern Japan Semiconductor Incorporated (Renesas Electronics Corporation), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kikuchi, Sakae, Kobayashi, Yoshihiko, Hashizume, Masakazu, Shiokawa, Yoshinori, Ida, Tsutomu
• Granted Patent: US 7,453,147 B2
• Time in Patent Office: Days
• US Class Current: 257/782
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48639 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48647 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/75745 in the upper part of the bonding apparatus, e.g. in the bonding head
• CPC Class Codes: H01L 2224/78 : Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/81143 : Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83801 : Soldering or alloying
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/85205 : Ultrasonic bonding
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H03F 2200/111 : the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 3/245 : with semiconductor devices only
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.

Claims

1-37. -37. (canceled)

38. A semiconductor device, comprising:

a wiring substrate;

a plurality of semiconductor chips, in each of which a field-effect transistor is built, each of said semiconductor chips being fixed over a metallized layer provided over a main surface of said wiring substrate with a fusion bonding material therebetween; and

a conductive wire for electrically connecting each of the gate electrode and the drain electrode of said semiconductor chip to a bonding pad formed over the main surface of said wiring substrate,

wherein each of said plurality of field-effect transistors is connected to another in order serially so as to configure each of a plurality of amplification stages of a multistage amplifier unit, and

wherein at least in one of said plurality of transistors, the drain wire for connecting said drain electrode to said bonding pad is set shorter than the gate wire for connecting said gate electrode to said bonding pad.

39. The semiconductor device according to claim 38,

wherein the distance between the drain electrode of said semiconductor chip and the edge of said semiconductor chip in a direction in which said drain wire is extended is shorter than the distance between the gate electrode of said semiconductor chip and the edge of said semiconductor chip in a direction in which said gate wire is extended.

40. The semiconductor device according to claim 38,

wherein a semiconductor chip provided between said gate bonding pad corresponding to said gate electrode and said drain bonding pad corresponding to said drain electrode is fixed at said wiring substrate one-sidedly closer to said drain bonding pad.

41. The semiconductor device according to claim 38,

wherein a recess is formed in a main surface of said wiring substrate and said semiconductor chip is fixed over a metallized layer formed at the bottom of said recess via the fusion bonding material.

42. The semiconductor device according to claim 41,

wherein one to two sides of said semiconductor chip are positioned so as to come in contact with an inner wall of said recess.

43. The semiconductor device according to claim 41,

wherein said metallized layer is extended up to the inner wall of said recess, which is closer to said drain bonding pad.

44. The semiconductor device according to claim 41,

wherein said metallized layer is formed all over the bottom of said recess and said fusion bonding material is disposed over part of said metallized layer.

45. The semiconductor device according to claim 38,

wherein said metallized layer is the same or approximately the same in size as said semiconductor chip and said fusion bonding material used to adhere said semiconductor chip to said metallized layer is also the same in size as said semiconductor chip.

46. The semiconductor device according to claim 38,

wherein said fusion bonding material is provided over part of said metallized layer and said semiconductor chip is positioned over this fusion bonding material.

47. The semiconductor device according to claim 38,

wherein, in said semiconductor chip, a fixing position is corrected and fixed over said metallized layer by the self-alignment action of said fusion bonding material at fusion of said material.

48. The semiconductor device according to claim 38,

wherein a wire length of the drain wire of the transistor in the final amplification stage of said multistage amplification unit is shorter than that of said gate wire.

49. The semiconductor device according to claim 38,

wherein a plurality of sets of said multistage amplifier units are formed.

50. The semiconductor device according to claim 49,

wherein the plural sets of multistage amplifier units are formed, and some or all the input terminals of said plurality of multistage amplifier units are common while the output terminals of said plurality of multistage amplifier units are independent of one another.

51. The semiconductor device according to claim 49,

wherein the plural sets of multistage amplifier units are formed, and both input and output terminals of each of said plurality of multistage amplifier units are independent of one another.

66. A radio communication device including a semiconductor device that uses a multistage amplifier unit at its transmission part,

wherein said semiconductor device is that according to said claim 38.

52. A semiconductor device, comprising:

a wiring substrate;

a plurality of semiconductor chips, in each of which a bipolar transistors is built, said each of said semiconductor chips being fixed over a metallized layer formed over a main surface of said wiring substrate with a fusion bonding material therebetween; and

a conductive wire for electrically connecting both base and collector electrodes of each of said plural semiconductor chips to bonding pads provided over said main surface of said wiring substrate,

wherein each of said plurality of bipolar transistors is connected to another in order serially so as to configure each of said plurality of amplification stages of each amplifier unit, and

wherein at least in one of said plurality of transistors, a length of the collector wire for connecting said collector electrode to said bonding pad is shorter than that of the base wire for connecting said base electrode to said bonding pad.

53. The semiconductor device according to claim 52,

wherein the distance between the collector electrode of said semiconductor chip and the edge of said semiconductor chip in a direction in which said collector wire is extended is shorter than the distance between the base electrode of said semiconductor chip and the edge of said semiconductor chip in a direction in which said base wire is extended.

54. The semiconductor device according to claim 52,

wherein a semiconductor chip positioned between said base bonding pad corresponding to said base electrode and said collector bonding pad corresponding to said collector electrode is fixed at said wiring substrate one-sidedly closer to said collector bonding pad.

55. The semiconductor device according to claim 52,

wherein a recess is formed in said main surface of said wiring substrate and said semiconductor chip is fixed over a metallized layer formed at the bottom of said recess via the fusion bonding material.

56. The semiconductor device according to claim 55,

wherein one to two sides of said semiconductor chip are positioned so as to come in contact with an inner wall of said recess.

57. The semiconductor device according to claim 55,

wherein said metallized layer is extended up to the inner wall of said recess, which is closer to said collector bonding pad.

58. The semiconductor device according to claim 55,

wherein said metallized layer is formed all over the bottom of said recess and said fusion bonding material is disposed over part of said metallized layer.

59. The semiconductor device according to claim 52,

wherein said metallized layer is the same or approximately the same in size as said semiconductor chip and said fusion bonding material for adhering said semiconductor chip to said metallized layer is also the same in size as said semiconductor chip.

60. The semiconductor device according to claim 52,

wherein said fusion bonding material is provided over part of said metallized layer and said semiconductor chip is positioned over this fusion bonding material.

61. The semiconductor device according to claim 52,

wherein, in said semiconductor chip, a fixing position is corrected and fixed over said metallized layer by the self-alignment action of said fusion bonding material at fusion of said material.

62. The semiconductor device according to claim 52,

wherein a wire length of the collector wire of the transistor in the final amplification stage of said multistage amplifier unit is shorter than that of the base wire thereof.

63. The semiconductor device according to claim 52,

wherein a plurality of sets of said multistage amplifier units are formed.

64. The semiconductor device according to claim 63,

wherein the plural sets of said multistage amplifier units are formed, and some or all the input terminals of said plurality of multistage amplifier units are common and the output terminals of said plurality of multistage amplifier units are independent of one another.

65. The semiconductor device according to claim 63,

wherein the plural sets of said multistage amplifier units are formed, and both input and output terminals of each of said plurality of multistage amplifier units are independent of one another.

67. A radio communication device including a semiconductor device that uses a multistage amplifier unit at its transmission part,

wherein said semiconductor device is that according to claim 52.